remove unneeded tests

diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index a22b0d6d8bf64ea2a435705927a0e4c123bf0315..789ac9cd01f0650d03fd1ea422ff46f2eb291c96 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -99,261 +99,6 @@ class DDFFirstTestCase(FHDLTestCase):
             self.assertEqual(sim.svstate.srcstep, 0)
             self.assertEqual(sim.svstate.dststep, 0)
 
-    def test_1(self):
-        lst = SVP64Asm(["sv.cmpi/ff=lt 0, 1, *10, 5"
-                        ])
-        lst = list(lst)
-
-        # SVSTATE
-        svstate = SVP64State()
-        vl = 3  # VL
-        svstate.vl = vl  # VL
-        svstate.maxvl = vl  # MAXVL
-        print("SVSTATE", bin(svstate.asint()))
-
-        gprs = [0] * 32
-        gprs[10] = 7
-        gprs[11] = 5
-        gprs[12] = 12
-
-        res = []
-        cr_res = [0]*8
-
-        newvl = sv_cmpi(gprs, cr_res, vl, 10, 5)
-        log("sv_cmpi", newvl, cr_res)
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs=gprs,
-                                       svstate=svstate)
-            for i in range(4):
-                val = sim.gpr(i).value
-                res.append(val)
-                cr_res.append(0)
-                print("i", i, val)
-            # confirm that the results are as expected
-            expected = deepcopy(vec)
-            expected_vl = 0
-            for i in range(4):
-                # calculate expected result and expected CR field
-                result = vec[i] - gprs[8]
-                crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
-                cr_res[i] = crf
-                if result <= 0:
-                    break
-                # VLi=0 - test comes FIRST!
-                expected[i] = result
-                # only write out if successful
-                expected_vl += 1
-
-            for i, v in enumerate(cr_res):
-                crf = sim.crl[i].get_range().value
-                print ("crf", i, res[i], bin(crf), bin(v))
-                self.assertEqual(crf, v)
-
-            for i, v in enumerate(res):
-                self.assertEqual(v, expected[i])
-
-            self.assertEqual(sim.svstate.vl, expected_vl)
-            self.assertEqual(sim.svstate.maxvl, 4)
-            self.assertEqual(sim.svstate.srcstep, 0)
-            self.assertEqual(sim.svstate.dststep, 0)
-
-    def test_sv_addi_ffirst_le(self):
-        lst = SVP64Asm(["sv.subf./ff=le *0,8,*0"
-                        ])
-        lst = list(lst)
-
-        # SVSTATE
-        svstate = SVP64State()
-        svstate.vl = 4  # VL
-        svstate.maxvl = 4  # MAXVL
-        print("SVSTATE", bin(svstate.asint()))
-
-        gprs = [0] * 64
-        gprs[8] = 3
-        vec = [9, 8, 3, 4]
-
-        res = []
-        cr_res = []
-        # store GPRs
-        for i, x in enumerate(vec):
-            gprs[i] = x
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs=gprs,
-                                       svstate=svstate)
-            for i in range(4):
-                val = sim.gpr(i).value
-                res.append(val)
-                cr_res.append(0)
-                print("i", i, val)
-            # confirm that the results are as expected
-            expected = deepcopy(vec)
-            expected_vl = 0
-            for i in range(4):
-                # calculate expected result and expected CR field
-                result = vec[i] - gprs[8]
-                crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
-                cr_res[i] = crf
-                if result <= 0:
-                    break
-                # VLi=0 - test comes FIRST!
-                expected[i] = result
-                # only write out if successful
-                expected_vl += 1
-
-            for i, v in enumerate(cr_res):
-                crf = sim.crl[i].get_range().value
-                print ("crf", i, res[i], bin(crf), bin(v))
-                self.assertEqual(crf, v)
-
-            for i, v in enumerate(res):
-                self.assertEqual(v, expected[i])
-
-            self.assertEqual(sim.svstate.vl, expected_vl)
-            self.assertEqual(sim.svstate.maxvl, 4)
-            self.assertEqual(sim.svstate.srcstep, 0)
-            self.assertEqual(sim.svstate.dststep, 0)
-
-    def test_sv_addi_ffirst(self):
-        lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0"
-                        ])
-        lst = list(lst)
-
-        # SVSTATE
-        svstate = SVP64State()
-        svstate.vl = 4  # VL
-        svstate.maxvl = 4  # MAXVL
-        print("SVSTATE", bin(svstate.asint()))
-
-        gprs = [0] * 64
-        gprs[8] = 3
-        vec = [9, 8, 3, 4]
-
-        res = []
-        cr_res = []
-        # store GPRs
-        for i, x in enumerate(vec):
-            gprs[i] = x
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs=gprs,
-                                       svstate=svstate)
-            for i in range(4):
-                val = sim.gpr(i).value
-                res.append(val)
-                cr_res.append(0)
-                print("i", i, val)
-            # confirm that the results are as expected
-            expected = deepcopy(vec)
-            for i in range(4):
-                result = vec[i] - gprs[8]
-                crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
-                cr_res[i] = crf
-                if result == 0:
-                    break
-                # VLi=0 - test comes FIRST!
-                expected[i] = result
-            for i, v in enumerate(cr_res):
-                crf = sim.crl[i].get_range().value
-                print ("crf", i, res[i], bin(crf), bin(v))
-                self.assertEqual(crf, v)
-
-            for i, v in enumerate(res):
-                self.assertEqual(v, expected[i])
-
-            self.assertEqual(sim.svstate.vl, 2)
-            self.assertEqual(sim.svstate.maxvl, 4)
-            self.assertEqual(sim.svstate.srcstep, 0)
-            self.assertEqual(sim.svstate.dststep, 0)
-
-    def test_sv_addi_ffirst_rc1(self):
-        lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0"  # RC1 auto-sets EQ (and Rc=1)
-                        ])
-        lst = list(lst)
-
-        # SVSTATE
-        svstate = SVP64State()
-        svstate.vl = 4  # VL
-        svstate.maxvl = 4  # MAXVL
-        print("SVSTATE", bin(svstate.asint()))
-
-        gprs = [0] * 64
-        gprs[8] = 3
-        vec = [9, 8, 3, 4]
-
-        res = []
-        # store GPRs
-        for i, x in enumerate(vec):
-            gprs[i] = x
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs=gprs,
-                                       svstate=svstate)
-            for i in range(4):
-                val = sim.gpr(i).value
-                res.append(val)
-                print("i", i, val)
-            # confirm that the results are as expected
-            expected = deepcopy(vec)
-            for i in range(4):
-                result = expected[i] - gprs[8]
-                if result == 0:
-                    break
-                # VLi=0 - test comes FIRST!
-                expected[i] = result
-            for i, v in enumerate(res):
-                self.assertEqual(v, expected[i])
-
-            self.assertEqual(sim.svstate.vl, 2)
-            self.assertEqual(sim.svstate.maxvl, 4)
-            self.assertEqual(sim.svstate.srcstep, 0)
-            self.assertEqual(sim.svstate.dststep, 0)
-
-    def test_sv_addi_ffirst_vli(self):
-        """data-dependent fail-first with VLi=1, the test comes *after* write
-        """
-        lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
-                        ])
-        lst = list(lst)
-
-        # SVSTATE
-        svstate = SVP64State()
-        svstate.vl = 4  # VL
-        svstate.maxvl = 4  # MAXVL
-        print("SVSTATE", bin(svstate.asint()))
-
-        gprs = [0] * 64
-        gprs[8] = 3
-        vec = [9, 8, 3, 4]
-
-        res = []
-        # store GPRs
-        for i, x in enumerate(vec):
-            gprs[i] = x
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs=gprs,
-                                       svstate=svstate)
-            for i in range(4):
-                val = sim.gpr(i).value
-                res.append(val)
-                print("i", i, val)
-            # confirm that the results are as expected
-            expected = deepcopy(vec)
-            for i in range(4):
-                # VLi=1 - test comes AFTER write!
-                expected[i] -= gprs[8]
-                if expected[i] == 0:
-                    break
-            for i, v in enumerate(res):
-                self.assertEqual(v, expected[i])
-
-            self.assertEqual(sim.svstate.vl, 3)
-            self.assertEqual(sim.svstate.maxvl, 4)
-            self.assertEqual(sim.svstate.srcstep, 0)
-            self.assertEqual(sim.svstate.dststep, 0)
-
     def run_tst_program(self, prog, initial_regs=None,
                         svstate=None,
                         initial_mem=None,