* rl78-decode.opc: Fix encoding of DIVWU insn.

	* rl78-decode.c: Regenerate.

	* config/rl78-parse.y: Fix encoding of DIVWU insn.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f9c8618a0231bffc7badb7ae05b6f7b6a4dd304f..0014922e89f377256cd9f013d3200d79f130f623 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
+
+       * config/rl78-parse.y: Fix encoding of DIVWU insn.
+
 2013-02-25  Terry Guo  <terry.guo@arm.com>
 
        * config/tc-arm.c (arm_cpus): Add cortex-r7 entry.

diff --git a/gas/config/rl78-parse.y b/gas/config/rl78-parse.y
index b487312f5a740cd0ec782ea10cea3c9a9415fcc7..1f01920ce0f9a3f0c6647f3d69d971bcec62196b 100644 (file)
--- a/gas/config/rl78-parse.y
+++ b/gas/config/rl78-parse.y
@@ -1,6 +1,5 @@
 /* rl78-parse.y  Renesas RL78 parser
-   Copyright 2011
-   Free Software Foundation, Inc.
+   Copyright 2011-2013 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -513,8 +512,13 @@ statement :
        | DIVHU
          { B3 (0xce, 0xfb, 0x03); }
 
+/* Note that the DIVWU encoding was changed from [0xce,0xfb,0x04] to
+   [0xce,0xfb,0x0b].  Different versions of the Software Manual exist
+   with the same version number, but varying encodings.  The version
+   here matches the hardware.  */
+
        | DIVWU
-         { B3 (0xce, 0xfb, 0x04); }
+         { B3 (0xce, 0xfb, 0x0b); }
 
        | MACHU
          { B3 (0xce, 0xfb, 0x05); }

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3e75abf35dcee0651688b484cced011d6b85e340..fdb1ed618f3f35ad367580ee801cc0ec47ef25e9 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
+
+       * rl78-decode.opc: Fix encoding of DIVWU insn.
+       * rl78-decode.c: Regenerate.
+
 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/15159

diff --git a/opcodes/rl78-decode.c b/opcodes/rl78-decode.c
index fab973cb9b51f65d47aa2431d904cfc91b836530..46531f5b3ffef608eac3ec051b6d5fbd05a8d7d3 100644 (file)
--- a/opcodes/rl78-decode.c
+++ b/opcodes/rl78-decode.c
@@ -1,6 +1,6 @@
 #line 1 "rl78-decode.opc"
 /* -*- c -*- */
-/* Copyright 2012 Free Software Foundation, Inc.
+/* Copyright 2012-2013 Free Software Foundation, Inc.
    Contributed by Red Hat.
    Written by DJ Delorie.
 
@@ -5167,7 +5167,7 @@ rl78_decode_opcode (unsigned long pc AU,
                rl78->syntax = "divhu"; ID(divhu);
                break;
               case 0x04:
-               rl78->syntax = "divwu"; ID(divwu);
+               rl78->syntax = "divwu <old-encoding>"; ID(divwu);
                break;
               case 0x05:
                rl78->syntax = "machu"; ID(machu);
@@ -5175,9 +5175,11 @@ rl78_decode_opcode (unsigned long pc AU,
               case 0x06:
                rl78->syntax = "mach"; ID(mach);
                break;
+              case 0x0b:
+               rl78->syntax = "divwu"; ID(divwu);
+               break;
               }
-        
-        }
+         }
       break;
     case 0xcf:
         {

diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc
index 11bfc4e821e4ab39b08e41a7351b997fcefd899a..901e1b39303f4d58e174ec065c44d1c722ce3cf2 100644 (file)
--- a/opcodes/rl78-decode.opc
+++ b/opcodes/rl78-decode.opc
@@ -1,5 +1,5 @@
 /* -*- c -*- */
-/* Copyright 2012 Free Software Foundation, Inc.
+/* Copyright 2012-2013 Free Software Foundation, Inc.
    Contributed by Red Hat.
    Written by DJ Delorie.
 
@@ -762,7 +762,7 @@ rl78_decode_opcode (unsigned long pc AU,
        rl78->syntax = "divhu"; ID(divhu);
        break;
       case 0x04:
-       rl78->syntax = "divwu"; ID(divwu);
+       rl78->syntax = "divwu <old-encoding>" ID(divwu);
        break;
       case 0x05:
        rl78->syntax = "machu"; ID(machu);
@@ -770,6 +770,9 @@ rl78_decode_opcode (unsigned long pc AU,
       case 0x06:
        rl78->syntax = "mach"; ID(mach);
        break;
+      case 0x0b:
+       rl78->syntax = "divwu"; ID(divwu);
+       break;
       }
 
 /** 1001 1110                  mov     %0, %1                          */