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+Date: Tue, 12 May 2020 12:12:39 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-304-13-QeaiztsorL@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-304-13@https.bugs.libre-soc.org/>
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+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 304] Define minimum viable interface set for
+ 180nm ASIC
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