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raw | patch | inline | side by side (parent: 08fe7a7)
Remove all uses of M1.
authorNick Clifton <nickc@redhat.com>
Sun, 3 Dec 2000 21:58:27 +0000 (21:58 +0000)
committerNick Clifton <nickc@redhat.com>
Sun, 3 Dec 2000 21:58:27 +0000 (21:58 +0000)
opcodes/ChangeLog patch | blob | history
opcodes/mips-opc.c patch | blob | history

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6232735b53e914c97c4cc368a248a12d057fd2f3..4c8972f287ca70d756e2c51bdcbd080820aad7a1 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -3,6 +3,9 @@
         * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
         MOD_HILO, and MOD_LO macros.
 
+        * mips-opc.c (M1, M2): Delete.
+        (mips_builtin_opcodes): Remove all uses of M1.
+
 2000-12-03  Ed Satterthwaite  ehs@sibyte.com  and
             Chris Demetriou   cgd@sibyte.com
 
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 86a58fa1345967c3ed87bf3f63d7c22f82b842c4..81aaf33f27a1bef8b293d9f1be4c2cc0ab3ef0d0 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -97,9 +97,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 
 #define G6      INSN_GP32
 
-#define M1      0
-#define M2      0
-
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -116,9 +113,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,      match,      mask,       pinfo,                  membership */
-{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  I32|G3|M1},
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  I32|G3  },
 {"nop",     "",         0x00000000, 0xffffffff, 0,                     I1      },
-{"ssnop",   "",         0x00000040, 0xffffffff, 0,                     I32|M1  },
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,                     I32     },
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                  I1      }, /* addiu */
 {"li",     "t,i",      0x34000000, 0xffe00000, WR_t,                   I1      }, /* ori */
 {"li",      "t,I",     0,    (int) M_LI,       INSN_MACRO,             I1      },
@@ -151,10 +148,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* bal is at the top of the table.  */
 {"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,              I1      },
 {"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
-{"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         I1|M1   },
-{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,        I4|I32|M1},
-{"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3|M1},
-{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,        I4|I32|M1},
+{"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         I1      },
+{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,        I4|I32  },
+{"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3   },
+{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,        I4|I32  },
 {"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,              I1      },
 {"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
 {"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,              I1      },
@@ -162,9 +159,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              I1      },
 {"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
 {"bc1t",    "p",       0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         I1      },
-{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,        I4|I32|M1},
+{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,        I4|I32  },
 {"bc1tl",   "p",       0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3   },
-{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,        I4|I32|M1},
+{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,        I4|I32  },
 {"bc2t",    "p",       0x49010000, 0xffff0000, CBD|RD_CC,              I1      },
 {"bc2tl",   "p",       0x49030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
 {"bc3t",    "p",       0x4d010000, 0xffff0000, CBD|RD_CC,              I1      },
@@ -230,102 +227,102 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"break",   "c",       0x0000000d, 0xfc00ffff, TRAP,                   I1      },
 {"break",   "c,q",     0x0000000d, 0xfc00003f, TRAP,                   I1      },
 {"c.f.d",   "S,T",     0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
-{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32|M1},
+{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32|M1},
+{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
 {"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
-{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                  I3|I32|T3|M1},
+{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                  I3|I32|T3},
 {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
 {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
@@ -365,7 +362,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* dctr and dctw are used on the r5000.  */
 {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,                   I3      },
 {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,                   I3      },
-{"deret",   "",         0x4200001f, 0xffffffff, 0,                     I32|G2|M1},
+{"deret",   "",         0x4200001f, 0xffffffff, 0,                     I32|G2  },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
 {"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,             I3      },
@@ -437,7 +434,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,             I3      },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             I3      },
-{"eret",    "",         0x42000018, 0xffffffff, 0,                     I3|I32|M1},
+{"eret",    "",         0x42000018, 0xffffffff, 0,                     I3|I32  },
 {"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
 {"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
 {"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
@@ -536,18 +533,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
-{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
-{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
-{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
-{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,             L1      },
-{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,            I32     },
-{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,        G1|M1   },
-{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M,    G1      },
-{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,             L1      },
-{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,            I32     },
-{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,        G1|M1   },
-{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M,    G1     },
-{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,            V1      },
+{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I4 },
+{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    I4 },
+{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I5 },
+{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32},
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1 },
+{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
+{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32},
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1        },
+{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1        },
+{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          V1 },
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         I1      },
 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        I32     },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1      },
@@ -562,26 +559,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
 {"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
-{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32|M1},
-{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32|M1},
-{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32|M1},
+{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
+{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32 },
+{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32 },
 {"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
-{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        I4|I32|M1},
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        I4|I32  },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,              L1      },
-{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32|M1},
-{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32|M1},
-{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|I32|M1},
-{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32|M1},
-{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32|M1},
+{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32 },
+{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32 },
+{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|I32 },
+{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32 },
+{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32 },
 {"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
-{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        I4|I32|M1},
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        I4|I32  },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,              L1      },
-{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32|M1},
-{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32|M1},
+{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32 },
+{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32 },
 /* move is at the top of the table.  */
-{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
-{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
-{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
+{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
+{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
+{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     L1      },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,     L1      },
@@ -616,12 +613,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
 {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
 {"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
-{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
-{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
-{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
-{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
-{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
-{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
+{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
+{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
+{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
+{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
+{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
+{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
 /* nop is at the start of the table.  */
 {"nor",     "d,v,t",   0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
 {"nor",     "t,r,I",   0,    (int) M_NOR_I,    INSN_MACRO,             I1      },
@@ -667,9 +664,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sd",     "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
 {"sd",      "t,o(b)",  0,    (int) M_SD_OB,    INSN_MACRO,             I1      },
 {"sd",      "t,A(b)",  0,    (int) M_SD_AB,    INSN_MACRO,             I1      },
-{"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,                   G2|M1   },
-{"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,                   G2|M1   },
-{"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,                   G2|M1   },
+{"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,                   G2      },
+{"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,                   G2      },
+{"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,                   G2      },
 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                  I32     },
 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                  I32     },
 {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
@@ -779,10 +776,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
 {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,             I2      },
-{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,              I1|M1   },
-{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,              I1|M1   },
-{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,              I1|M1   },
-{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,              I1|M1   },
+{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,              I1      },
+{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,              I1      },
+{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,              I1      },
+{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,              I1      },
 {"tlti",    "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,              I2      },
 {"tlt",     "s,t",     0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
 {"tlt",     "s,t,q",   0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
@@ -823,7 +820,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             I1      },
 {"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,              I1      },
-{"wait",    "",         0x42000020, 0xffffffff, TRAP,                  I3|I32|M1},
+{"wait",    "",         0x42000020, 0xffffffff, TRAP,                  I3|I32  },
 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                  I32     },
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,                   L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                L1      },