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@@ -6,6 +6,7 @@
 * Revision 0.9 pre-final: 18 Apr 2020
 * Revision 0.91 mention dual ISA: 22 Apr 2020
 * Revision 0.92 mention countdown idea: 22 Apr 2020
+* Revision 0.93 illegal instruction trap: 27 Apr 2020
 
 ## Why has Libre-SOC chosen PowerPC ?
 
@@ -79,6 +80,8 @@ The available space in a suitably-chosen SPR to be formalised, and
 recommend the OpenPOWER Foundation be given the IANA-like role in
 atomically allocating mode bits.
 
+The IANA-like atomic role ensures that new PCR mode bits are allocated world-wide unique.  In combination with a mandatory illegal instruction exception to be thrown on any system not supporting any given mode, the opportunity exists for all systems to trap and emulate all other systems and thus retain some semblance of interoperability.  (*Contrast this with either allocating the same mode bit(s) to two (or more) designers, or not making illegal exceptions mandarory: binary interoperability becomes unachievable and the result is irrevocable damage to POWER's reputation.*)
+
 We also advocate to consider reserving some bits as a "countdown" where the new mode will be enabled only for a certain *number* of instructions. This avoids an explicit need to "flip back", reducing binary code size. Note that it is not a good idea to let the counter cross a branch or other change in PC (and to throw illegal instruction trap if attempted). However traps and exceptions themselves will need to save (and restore) the countdown, just as the rest of the PCR and other modeswitching bits need to be saved.
 
 Instructions that we need to add, which are a normal part of GPUs,