Handle newer nMigen adding a "bench" top-level root in VCD files

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index cf9b28b3615bae44be508337fc6e3adfe0e92beb..4068d1ab10c117f348ff0dc8eca62ed7c276fd59 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -534,7 +534,7 @@ class TestRunnerBase(FHDLTestCase):
 
         write_gtkw("%s.gtkw" % gtkname,
                    "%s.vcd" % gtkname,
-                   traces, styles, module='top.issuer')
+                   traces, styles, module='bench.top.issuer')
 
         # add run of instructions
         sim.add_sync_process(process)