def __init__(self, mac_address, ip_address):
self.sink = sink = Sink(_arp_table_layout)
self.source = source = Source(eth_mac_description(8))
- ###
+
+ # # #
+
self.submodules.packetizer = packetizer = LiteEthARPPacketizer()
counter = Counter(max=max(arp_header_len, eth_min_len))
def __init__(self, mac_address, ip_address):
self.sink = sink = Sink(eth_mac_description(8))
self.source = source = Source(_arp_table_layout)
- ###
+
+ # # #
+
self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer()
self.comb += Record.connect(sink, depacketizer.sink)
class LiteEthARPTable(Module):
def __init__(self, clk_freq, max_requests=8):
self.sink = sink = Sink(_arp_table_layout) # from arp_rx
- self.source = source = Source(_arp_table_layout) # to arp_tx
+ self.source = source = Source(_arp_table_layout) # to arp_tx
# Request/Response interface
self.request = request = Sink(arp_table_request_layout)
self.response = response = Source(arp_table_response_layout)
- ###
+
+ # # #
+
request_timeout = Timeout(clk_freq//10)
request_counter = Counter(max=max_requests)
request_pending = FlipFlop()
def __init__(self, udp_port):
self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
self.source = source = Source(eth_udp_user_description(32))
- ###
+
+ # # #
+
self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer()
self.comb += [
packetizer.sink.stb.eq(sink.stb),
def __init__(self):
self.sink = sink = Sink(eth_udp_user_description(32))
self.source = source = Source(eth_etherbone_packet_user_description(32))
- ###
+
+ # # #
+
self.submodules.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer()
self.comb += Record.connect(sink, depacketizer.sink)
def __init__(self):
self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
self.source = source = Source(eth_etherbone_packet_user_description(32))
- ###
+
+ # # #
+
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
sink.ack.eq(1),
def __init__(self, buffer_depth=256):
self.sink = sink = Sink(eth_etherbone_record_description(32))
self.source = source = Source(eth_etherbone_mmap_description(32))
- ###
+
+ # # #
+
fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True)
self.submodules += fifo
self.comb += Record.connect(sink, fifo.sink)
def __init__(self, buffer_depth=256):
self.sink = sink = Sink(eth_etherbone_mmap_description(32))
self.source = source = Source(eth_etherbone_record_description(32))
- ###
+
+ # # #
+
pbuffer = PacketBuffer(eth_etherbone_mmap_description(32), buffer_depth)
self.submodules += pbuffer
self.comb += Record.connect(sink, pbuffer.sink)
def __init__(self, endianness="big"):
self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
self.source = source = Sink(eth_etherbone_packet_user_description(32))
- ###
+
+ # # #
# receive record, decode it and generate mmap stream
self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
self.sink = sink = Sink(eth_etherbone_mmap_description(32))
self.source = source = Source(eth_etherbone_mmap_description(32))
self.bus = bus = wishbone.Interface()
- ###s
+
+ # # #
self.submodules.data = data = FlipFlop(32)
self.comb += data.d.eq(bus.dat_r)
def __init__(self, ip_address):
self.sink = sink = Sink(eth_icmp_user_description(8))
self.source = source = Source(eth_ipv4_user_description(8))
- ###
+
+ # # #
+
self.submodules.packetizer = packetizer = LiteEthICMPPacketizer()
self.comb += [
packetizer.sink.stb.eq(sink.stb),
def __init__(self, ip_address):
self.sink = sink = Sink(eth_ipv4_user_description(8))
self.source = source = Source(eth_icmp_user_description(8))
- ###
+
+ # # #
+
self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer()
self.comb += Record.connect(sink, depacketizer.sink)
def __init__(self):
self.sink = sink = Sink(eth_icmp_user_description(8))
self.source = source = Source(eth_icmp_user_description(8))
- ###
+
+ # # #
+
self.submodules.buffer = PacketBuffer(eth_icmp_user_description(8), 128, 2)
self.comb += [
Record.connect(sink, self.buffer.sink),
self.sink = sink = Sink(eth_ipv4_user_description(8))
self.source = source = Source(eth_mac_description(8))
self.target_unreachable = Signal()
- ###
+
+ # # #
+
self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
self.comb += [
checksum.ce.eq(sink.stb & sink.sop),
def __init__(self, mac_address, ip_address):
self.sink = sink = Sink(eth_mac_description(8))
self.source = source = Source(eth_ipv4_user_description(8))
- ###
+
+ # # #
+
self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer()
self.comb += Record.connect(sink, depacketizer.sink)
self.header = Signal(ipv4_header_len*8)
self.value = Signal(16)
self.done = Signal()
- ###
+
+ # # #
+
s = Signal(17)
r = Signal(17)
n_cycles = 0
def __init__(self, ip_address, udp_port, fifo_depth=None):
self.sink = sink = Sink(eth_tty_description(8))
self.source = source = Source(eth_udp_user_description(8))
- ###
+
+ # # #
+
if fifo_depth is None:
self.comb += [
source.stb.eq(sink.stb),
def __init__(self, ip_address, udp_port, fifo_depth=None):
self.sink = sink = Sink(eth_udp_user_description(8))
self.source = source = Source(eth_tty_description(8))
- ###
+
+ # # #
+
valid = Signal()
self.comb += valid.eq(
(sink.ip_address == ip_address) &
def __init__(self, ip_address):
self.sink = sink = Sink(eth_udp_user_description(8))
self.source = source = Source(eth_ipv4_user_description(8))
- ###
+
+ # # #
+
self.submodules.packetizer = packetizer = LiteEthUDPPacketizer()
self.comb += [
packetizer.sink.stb.eq(sink.stb),
def __init__(self, ip_address):
self.sink = sink = Sink(eth_ipv4_user_description(8))
self.source = source = Source(eth_udp_user_description(8))
- ###
+
+ # # #
+
self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer()
self.comb += Record.connect(sink, depacketizer.sink)
wb.open()
regs = wb.regs
- ###
-
+ # # #
conditions = {}
la.configure_term(port=0, cond=conditions)
la.configure_sum("term")
la.upload()
la.save("dump.vcd")
-
- ###
+ # # #
wb.close()
def main(wb):
wb.open()
regs = wb.regs
- ###
+ # # #
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
- ###
+ # # #
wb.close()
self.sink = sink = Sink(description)
self.source = source = Source(description)
- ###
+ # # #
+
sink_status = EndpointPacketStatus(self.sink)
source_status = EndpointPacketStatus(self.source)
self.submodules += sink_status, source_status
self.sink = sink = Sink(sink_description)
self.source = source = Source(source_description)
self.header = Signal(header_length*8)
- ###
+
+ # # #
+
dw = flen(sink.data)
header_words = (header_length*8)//dw
self.sel = Signal(len(sinks))
else:
self.sel = Signal(max=len(sinks))
- ###
+
+ # # #
+
sop = Signal()
self.comb += sop.eq(source.stb & source.sop)
sel = Signal(flen(self.sel))
self.sink = sink = Sink(sink_description)
self.source = source = Source(source_description)
self.header = Signal(header_length*8)
- ###
+
+ # # #
+
dw = flen(self.sink.data)
header_reg = Signal(header_length*8)
self.last = Signal(width)
self.next = Signal(width)
- ###
+ # # #
def _optimize_eq(l):
"""
self.value = Signal(self.width)
self.error = Signal()
- ###
+ # # #
self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
reg = Signal(self.width, reset=self.init)
self.source = source = Source(description)
self.busy = Signal()
- ###
+ # # #
dw = flen(sink.data)
crc = crc_class(dw)
self.source = source = Source(description)
self.busy = Signal()
- ###
+ # # #
dw = flen(sink.data)
crc = crc_class(dw)
def __init__(self, dw, ack_on_gap=False):
self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_phy_description(dw))
- ###
+
+ # # #
+
gap = math.ceil(eth_interpacket_gap/(dw//8))
self.submodules.counter = counter = Counter(max=gap)
def __init__(self, dw):
self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_phy_description(dw))
- ###
+
+ # # #
+
ongoing = Signal()
self.sync += \
If(sink.stb & sink.ack,
def __init__(self, dw):
self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_phy_description(dw))
- ###
+
+ # # #
+
self.comb += [
source.stb.eq(sink.stb),
source.sop.eq(sink.sop),
def __init__(self, dw, packet_min_length):
self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_phy_description(dw))
- ###
+
+ # # #
+
packet_min_data = math.ceil(packet_min_length/(dw/8))
self.submodules.counter = counter = Counter(max=eth_mtu)
def __init__(self, dw, packet_min_length):
self.sink = sink = Sink(eth_phy_description(dw))
self.source = source = Source(eth_phy_description(dw))
- ###
+
+ # # #
+
# XXX see if we should drop the packet when
# payload size < minimum ethernet payload size
self.comb += Record.connect(sink, source)
self.sink = Sink(eth_phy_description(dw))
self.source = Source(eth_phy_description(dw))
- ###
+ # # #
preamble = Signal(64, reset=eth_preamble)
cnt_max = (64//dw)-1
self.sink = Sink(eth_phy_description(dw))
self.source = Source(eth_phy_description(dw))
- ###
+ # # #
preamble = Signal(64, reset=eth_preamble)
cnt_max = (64//dw) - 1
self.ev.available = EventSourceLevel()
self.ev.finalize()
- ###
+ # # #
# packet dropped if no slot available
sink.ack.reset = 1
self.ev.done = EventSourcePulse()
self.ev.finalize()
- ###
+ # # #
# command fifo
fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
self.sink = Sink(eth_phy_description(dw))
self.source = Source(eth_phy_description(dw))
self.bus = wishbone.Interface()
- ###
+
+ # # #
+
# storage in SRAM
sram_depth = buffer_depth//(dw//8)
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
class LiteEthPHYGMIITX(Module):
def __init__(self, pads, pads_register):
self.sink = sink = Sink(eth_phy_description(8))
- ###
+
+ # # #
+
if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0)
pads_eq = [
class LiteEthPHYGMIIRX(Module):
def __init__(self, pads):
self.source = source = Source(eth_phy_description(8))
- ###
+
+ # # #
+
dv_d = Signal()
self.sync += dv_d.eq(pads.dv)
class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
self._reset = CSRStorage()
- ###
+
+ # # #
+
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
class LiteEthPHYGMIIMIITX(Module):
def __init__(self, pads, mode):
self.sink = sink = Sink(eth_phy_description(8))
- ###
+
+ # # #
+
gmii_tx_pads = Record(tx_pads_layout)
gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
self.submodules += gmii_tx
class LiteEthPHYGMIIMIIRX(Module):
def __init__(self, pads, mode):
self.source = source = Source(eth_phy_description(8))
- ###
+
+ # # #
+
pads_d = Record(rx_pads_layout)
self.sync += [
pads_d.dv.eq(pads.dv),
def __init__(self):
self._reset = CSRStorage()
self._value = CSRStatus(32)
- ###
+
+ # # #
+
counter = RenameClockDomains(Counter(32), "eth_rx")
self.submodules += counter
self.comb += [
class LiteEthPHYLoopbackCRG(Module, AutoCSR):
def __init__(self):
self._reset = CSRStorage()
- ###
+
+ # # #
+
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += [
class LiteEthPHYMIITX(Module):
def __init__(self, pads, pads_register=True):
self.sink = sink = Sink(eth_phy_description(8))
- ###
+
+ # # #
+
if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0)
converter = Converter(converter_description(8), converter_description(4))
class LiteEthPHYMIIRX(Module):
def __init__(self, pads):
self.source = source = Source(eth_phy_description(8))
- ###
+
+ # # #
+
sop = FlipFlop(reset=1)
self.submodules += sop
class LiteEthPHYMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset):
self._reset = CSRStorage()
- ###
+
+ # # #
+
if hasattr(clock_pads, "phy"):
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
def __init__(self):
self._reset = CSRStorage()
- ###
+ # # #
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
def __init__(self, description, last_be=None):
self.source = Source(description)
self.last_be = last_be
- ###
+
+ # # #
+
self.packets = []
self.packet = Packet()
self.packet.done = True
class PacketLogger(Module):
def __init__(self, description):
self.sink = Sink(description)
- ###
+
+ # # #
+
self.packet = Packet()
def receive(self):
packet = ARPPacket(packet)
# check decoding
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_request_infos)
# check encoding
packet.encode()
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_request_infos)
# ARP Reply
packet = ARPPacket(packet)
# check decoding
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_reply_infos)
# check encoding
packet.encode()
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_reply_infos)
print("arp errors " + str(errors))
packet.nr = 0
packet.pr = 0
packet.pf = 0
- #print(packet)
+ # print(packet)
packet.encode()
- #print(packet)
+ # print(packet)
# Send packet over UDP to check against Wireshark dissector
import socket
# ICMP packet
packet = MACPacket(ping_request)
packet.decode_remove_header()
- #print(packet)
+ # print(packet)
packet = IPPacket(packet)
packet.decode()
- #print(packet)
+ # print(packet)
packet = ICMPPacket(packet)
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, ping_request_infos)
packet.encode()
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, ping_request_infos)
print("icmp errors " + str(errors))
# UDP packet
packet = MACPacket(udp)
packet.decode_remove_header()
- #print(packet)
+ # print(packet)
packet = IPPacket(packet)
# check decoding
errors += not packet.check_checksum()
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, {})
# check encoding
packet.encode()
packet.insert_checksum()
errors += not packet.check_checksum()
packet.decode()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, {})
print("ip errors " + str(errors))
errors = 0
packet = MACPacket(arp_request)
packet.decode_remove_header()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_request_infos)
packet.encode_header()
packet.decode_remove_header()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_request_infos)
- #print(packet)
+ # print(packet)
packet = MACPacket(arp_reply)
packet.decode_remove_header()
errors += verify_packet(packet, arp_reply_infos)
packet.encode_header()
packet.decode_remove_header()
- #print(packet)
+ # print(packet)
errors += verify_packet(packet, arp_reply_infos)
print("mac errors " + str(errors))
# UDP packet
packet = MACPacket(udp)
packet.decode_remove_header()
- #print(packet)
+ # print(packet)
packet = IPPacket(packet)
packet.decode()
- #print(packet)
+ # print(packet)
packet = UDPPacket(packet)
packet.decode()
- #print(packet)
+ # print(packet)
if packet.length != (len(packet)+udp_header_len):
errors += 1
errors += verify_packet(packet, udp_infos)
packet.encode()
packet.decode()
- #print(packet)
+ # print(packet)
if packet.length != (len(packet)+udp_header_len):
errors += 1
errors += verify_packet(packet, udp_infos)
projects / litex.git / commitdiff