Merge remote-tracking branch 'origin/xaig' into xc7mux

diff --cc passes/techmap/abc9.cc
Simple merge

diff --cc techlibs/xilinx/abc_xc7.box
Simple merge

diff --cc techlibs/xilinx/cells_sim.v
index 29abc98077b0c3f8894cde14c8133d7084598782,8261286af8efcb0589891123e6ede21d2b7aae8d..c6c49c3cd3eab2587d1725e322d2bab01aefbbec
--- 1/techlibs/xilinx/cells_sim.v
--- 2/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -289,23 -281,7 +289,24 @@@ module FDPE_1 (output reg Q, input C, C
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
 +module RAM32X1D (
 +  output DPO, SPO,
 +  input  D, WCLK, WE,
 +  input  A0, A1, A2, A3, A4,
 +  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
 +);
 +  parameter INIT = 32'h0;
 +  parameter IS_WCLK_INVERTED = 1'b0;
 +  wire [4:0] a = {A4, A3, A2, A1, A0};
 +  wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 +  reg [31:0] mem = INIT;
 +  assign SPO = mem[a];
 +  assign DPO = mem[dpra];
 +  wire clk = WCLK ^ IS_WCLK_INVERTED;
 +  always @(posedge clk) if (WE) mem[a] <= D;
 +endmodule
 +
+ (* abc_box_id = 4, abc_scc_break="D" *)
  module RAM64X1D (
    output DPO, SPO,
    input  D, WCLK, WE,