integration/soc: add auto_int type and use it on all int parameters.

Allow passing parameters as int or hex values.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 8bbd4d2b272ca2986cbc812424e2dbd8111a2a05..b5b8575f04da8951cf83b48494d8b60236c313e5 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -27,6 +27,10 @@ from litex.soc.interconnect import axi
 logging.basicConfig(level=logging.INFO)
 
 # Helpers ------------------------------------------------------------------------------------------
+
+def auto_int(x):
+    return int(x, 0)
+
 def colorer(s, color="bright"):
     header  = {
         "bright": "\x1b[1m",

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 776ceee0070927927e869a06f943debd729fed12..7bf9faf2d29400bfc6c91b8cbbb40d418a174bde 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -255,25 +255,25 @@ def soc_core_args(parser):
                         help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
     parser.add_argument("--cpu-variant", default=None,
                         help="select CPU variant, (default=standard)")
-    parser.add_argument("--cpu-reset-address", default=None, type=int,
+    parser.add_argument("--cpu-reset-address", default=None, type=auto_int,
                         help="CPU reset address (default=0x00000000 or ROM)")
     # ROM parameters
-    parser.add_argument("--integrated-rom-size", default=0x8000, type=int,
+    parser.add_argument("--integrated-rom-size", default=0x8000, type=auto_int,
                         help="size/enable the integrated (BIOS) ROM (default=32KB)")
     parser.add_argument("--integrated-rom-file", default=None, type=str,
                         help="integrated (BIOS) ROM binary file")
     # SRAM parameters
-    parser.add_argument("--integrated-sram-size", default=0x1000, type=int,
+    parser.add_argument("--integrated-sram-size", default=0x1000, type=auto_int,
                         help="size/enable the integrated SRAM (default=4KB)")
     # MAIN_RAM parameters
-    parser.add_argument("--integrated-main-ram-size", default=None, type=int,
+    parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int,
                         help="size/enable the integrated main RAM")
     # CSR parameters
-    parser.add_argument("--csr-data-width", default=None, type=int,
+    parser.add_argument("--csr-data-width", default=None, type=auto_int,
                         help="CSR bus data-width (8 or 32, default=8)")
-    parser.add_argument("--csr-address-width", default=14, type=int,
+    parser.add_argument("--csr-address-width", default=14, type=auto_int,
                         help="CSR bus address-width")
-    parser.add_argument("--csr-paging", default=0x800, type=int,
+    parser.add_argument("--csr-paging", default=0x800, type=auto_int,
                         help="CSR bus paging")
     # Identifier parameters
     parser.add_argument("--ident", default=None, type=str,
@@ -285,9 +285,9 @@ def soc_core_args(parser):
                         help="with UART (default=True)")
     parser.add_argument("--uart-name", default="serial", type=str,
                         help="UART type/name (default=serial)")
-    parser.add_argument("--uart-baudrate", default=None, type=int,
+    parser.add_argument("--uart-baudrate", default=None, type=auto_int,
                         help="UART baudrate (default=115200)")
-    parser.add_argument("--uart-fifo-depth", default=16, type=int,
+    parser.add_argument("--uart-fifo-depth", default=16, type=auto_int,
                         help="UART FIFO depth (default=16)")
     # Timer parameters
     parser.add_argument("--with-timer", default=None, type=bool,

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 9eecaa5678712c0d88d39d55c8d36859d38f0c57..f3392f37f9e781ef5fba9508f43409793b77b1cd 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -13,6 +13,7 @@ import inspect
 from migen import *
 
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import auto_int
 
 __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
 
@@ -52,13 +53,13 @@ class SoCSDRAM(SoCCore):
 def soc_sdram_args(parser):
     soc_core_args(parser)
     # L2 Cache
-    parser.add_argument("--l2-size", default=8192,
+    parser.add_argument("--l2-size", default=8192, type=auto_int,
                         help="L2 cache size (default=8192)")
-    parser.add_argument("--min-l2-data-width", default=128,
+    parser.add_argument("--min-l2-data-width", default=128, type=auto_int,
                         help="Minimum L2 cache datawidth (default=128)")
 
     # SDRAM
-    parser.add_argument("--max-sdram-size", default=0x40000000,
+    parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int,
                         help="Maximum SDRAM size mapped to the SoC (default=1GB))")
 
 def soc_sdram_argdict(args):