(no commit message)

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index c6c0556f67b98ad874b1e6e18b112b06736542ec..2423de2de2febb7ef99cf9c0f73c70feddb201e8 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -280,12 +280,14 @@ When `mm=0`:
 * `rmm`, like REMAP.SVme, has bit 0 
   correspond to mi0, bit 1 to mi1, bit 2 to mi2,
   bit 3 to mo0 and bit 4 to mi1
-* all SVSHAPEs and the REMAP SPR are first reset (initialised to zero)
+* all SVSHAPEs and the REMAP parts of SVSHAPE are first reset (initialised to zero)
 * for each bit set in the 5-bit `rmm`, in order, the first
   as-yet-unset SVSHAPE will be updated
   with the other operands in the instruction, and the REMAP
   SPR set.
 * If all 5 bits of `rmm` are set then both mi0 and mo1 use SVSHAPE0.
+* SVSTATE persistence bit is cleared
+* No other alterations to SVSTATE are carried out
 
 Example 1: if rmm=0b00110 then SVSHAPE0 and SVSHAPE1 are set up,
 and the REMAP SPR set so that mi1 uses SVSHAPE0 and mi2
@@ -296,6 +298,16 @@ Example 2: if rmm=0b10001 then again SVSHAPE0 and SVSHAPE1
 are set up, but the REMAP SPR is set so that mi0 uses SVSHAPE0
 and mo1 uses SVSHAPE1. REMAP.SVme=0b10001, REMAP.mi0=0, REMAP.mo1=1
 
+Rough algorithmic form:
+
+   marray = [mi0, mi1, mi2, mo0, mo1]
+   idx = 0
+   for bit = 0 to 4:
+       if not rmm[bit]: continue
+       setup(SVSHAPE[idx])
+       SVSTATE{marray[bit]} = idx
+       idx = (idx+1) modulo 4
+
 When `mm=1`:
 
 * bits 0-2 of `rmm` indicate an index selecting mi0-mo1