sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata...

diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py
index 02319b60465df9570819eac9b2a4ca53c1a320da..64da0cf41d2d8288cd8263fb8e67bb6bc6b28f1d 100644 (file)
--- a/misoclib/mem/sdram/phy/s6ddrphy.py
+++ b/misoclib/mem/sdram/phy/s6ddrphy.py
@@ -23,10 +23,10 @@ from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 
-class S6DDRPHY(Module):
+class S6HalfRateDDRPHY(Module):
     def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         if module.memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
-            raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
+            raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
         addressbits = flen(pads.a)
         bankbits = flen(pads.ba)
         databits = flen(pads.dq)
@@ -358,27 +358,35 @@ class S6DDRPHY(Module):
         #
         # DQ/DQS/DM control
         #
+
+        # write
+        wrdata_en = Signal()
+        self.comb += wrdata_en.eq(optree("|", [d_dfi[p].wrdata_en for p in range(nphases)]))
+
         if module.memtype == "DDR3":
             r_drive_dq = Signal(self.settings.cwl-1)
-            sd_sdram_half += r_drive_dq.eq(Cat(d_dfi[self.settings.wrphase].wrdata_en, r_drive_dq))
+            sd_sdram_half += r_drive_dq.eq(Cat(wrdata_en, r_drive_dq))
             self.comb += drive_dq.eq(r_drive_dq[self.settings.cwl-2])
         else:
-            self.comb += drive_dq.eq(d_dfi[self.settings.wrphase].wrdata_en)
+            self.comb += drive_dq.eq(wrdata_en)
 
-        d_dfi_wrdata_en = Signal()
-        sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.settings.wrphase].wrdata_en)
+        wrdata_en_d = Signal()
+        sd_sys += wrdata_en_d.eq(wrdata_en)
 
         r_dfi_wrdata_en = Signal(max(self.settings.cwl, self.settings.cl))
-        sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en))
+        sd_sdram_half += r_dfi_wrdata_en.eq(Cat(wrdata_en_d, r_dfi_wrdata_en))
 
         if module.memtype == "DDR3":
             self.comb += drive_dqs.eq(r_dfi_wrdata_en[self.settings.cwl-1])
         else:
             self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
 
+        # read
+        rddata_en = Signal()
+        self.comb += rddata_en.eq(optree("|", [d_dfi[p].rddata_en for p in range(nphases)]))
+
         rddata_sr = Signal(self.settings.read_latency)
-        sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency],
-            d_dfi[self.settings.rdphase].rddata_en))
+        sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency], rddata_en))
 
         for n, phase in enumerate(self.dfi.phases):
             self.comb += [

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 18f960c8738e0898ef9f1007adc2ea09a42057cf..ce07dd69bfee01b364008f4824a28de72ed9a149 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -82,11 +82,11 @@ class BaseSoC(SDRAMSoC):
         self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)
 
         if not self.integrated_main_ram_size:
-            self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
-                                                       MT46V32M16(self.clk_freq),
-                                                       rd_bitslip=0,
-                                                       wr_bitslip=3,
-                                                       dqs_ddr_alignment="C1")
+            self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
+                                                               MT46V32M16(self.clk_freq),
+                                                               rd_bitslip=0,
+                                                               wr_bitslip=3,
+                                                               dqs_ddr_alignment="C1")
             self.register_sdram_phy(self.ddrphy)
             self.comb += [
                 self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index c7bf8d03a4fee686bbd58de3a85776cfb0b7252f..fd9bd1cbe678ddffb2ca9a193acd27be80bb6edd 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -108,11 +108,11 @@ class BaseSoC(SDRAMSoC):
         self.submodules.crg = _CRG(platform, clk_freq)
 
         if not self.integrated_main_ram_size:
-            self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
-                                                       MT46H32M16(self.clk_freq),
-                                                       rd_bitslip=1,
-                                                       wr_bitslip=3,
-                                                       dqs_ddr_alignment="C1")
+            self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
+                                                               MT46H32M16(self.clk_freq),
+                                                               rd_bitslip=1,
+                                                               wr_bitslip=3,
+                                                               dqs_ddr_alignment="C1")
             self.comb += [
                 self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
                 self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),