SPARC: Adjust a few instructions to not write registers in initiateAcc.

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index c35b231ff7168accfc7da3f55db4d036a5e7a328..e34ca033f879143d19f3084a0bd67bc2d7e277e9 100644 (file)
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1231,16 +1231,14 @@ decode OP default Unknown::unknown()
             0x23: Load::lddf({{Frd.udw = Mem.udw;}});
             0x24: Store::stf({{Mem.uw = Frds.uw;}});
             0x25: decode RD {
-                0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
-                                     if (fault)
-                                         return fault;
-                                    Mem.uw = Fsr<31:0>;
-                                    Fsr = insertBits(Fsr,16,14,0);}});
-                0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
-                                     if (fault)
-                                         return fault;
-                                     Mem.udw = Fsr;
-                                     Fsr = insertBits(Fsr,16,14,0);}});
+                0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
+                                       if (fault)
+                                           return fault;
+                                       Mem.uw = Fsr<31:0>;}});
+                0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
+                                        if (fault)
+                                            return fault;
+                                        Mem.udw = Fsr;}});
                 default: FailUnimpl::stfsrOther();
             }
             0x26: stqf({{fault = new FpDisabled;}});

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index e3c043cf3601d164377bd3ab21bb2a9c4693a580..c7bb3e435a8cac8d853d31b0acbc57562dba040d 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -108,6 +108,16 @@ def format Store(code, *opt_flags) {{
              StoreFuncs, '', name, Name, 0, opt_flags)
 }};
 
+def format StoreFsr(code, *opt_flags) {{
+        code = filterDoubles(code)
+        (header_output,
+         decoder_output,
+         exec_output,
+         decode_block) = doMemFormat(code,
+             StoreFuncs, '', name, Name, 0, opt_flags,
+             'Fsr = insertBits(Fsr,16,14,0);')
+}};
+
 def format TwinLoad(code, *opt_flags) {{
         (header_output,
          decoder_output,

diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index f2a2327ee14be261c682be8c0b8b6599924a4156..31efb9cf6e8da2874208bac687126eec620c4d6b 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -264,11 +264,6 @@ def template StoreInitiateAcc {{
                 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
                         EA, %(asi_val)s, 0);
             }
-            if(fault == NoFault)
-            {
-                    //Write the resulting state to the execution context
-                %(op_wb)s;
-            }
             return fault;
         }
 }};
@@ -277,6 +272,15 @@ def template StoreCompleteAcc {{
         Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
                 Trace::InstRecord * traceData) const
         {
+            Fault fault = NoFault;
+            %(op_decl)s;
+
+            %(op_rd)s;
+            %(postacc_code)s;
+            if (fault == NoFault)
+            {
+                %(op_wb)s;
+            }
             return NoFault;
         }
 }};