Add CacheRepl trace flag and move a couple DPRINTFs to it.

--HG--
extra : convert_revision : 31724d19ebdf2cdc2a2bafff83d17845b3a0b183

diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 70fadb210335bd76dd661f72425830440fb3a77a..8573eb9bf191b28487518c7ed8b5be080c928d12 100644 (file)
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -47,6 +47,7 @@ baseFlags = [
     'BusBridge',
     'Cache',
     'CachePort',
+    'CacheRepl',
     'Chains',
     'Checker',
     'Clock',

diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 3269aa4db71d834c1bbea58182a07d9535b56735..0a8587c2061647388d846c93e4150385683a78b2 100644 (file)
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -173,7 +173,7 @@ LRU::findBlock(Addr addr, int &lat)
     if (blk != NULL) {
         // move this block to head of the MRU list
         sets[set].moveToHead(blk);
-        DPRINTF(Cache, "set %x: moving blk %x to MRU\n",
+        DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
                 set, regenerateBlkAddr(tag, set));
         if (blk->whenReady > curTick
             && blk->whenReady - curTick > hitLatency) {
@@ -208,7 +208,7 @@ LRU::findReplacement(Addr addr, PacketList &writebacks)
         ++sampledRefs;
         blk->refCount = 0;
 
-        DPRINTF(Cache, "set %x: selecting blk %x for replacement\n",
+        DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
                 set, regenerateBlkAddr(blk->tag, set));
     } else if (!blk->isTouched) {
         tagsInUse++;