transition(I, DMA_WRITE, ID_W) {
- dw_writeDMAData;
-// da_sendDMAAck;
+ v_allocateTBE;
qw_queueMemoryWBRequest_partial;
p_popIncomingDMARequestQueue;
}
transition(ID_W, Memory_Ack, I) {
+ dwt_writeDMADataFromTBE;
da_sendDMAAck;
+ w_deallocateTBE;
l_popMemQueue;
}
drp_sendDMAData;
c_clearOwner;
a_sendWriteBackAck;
- // d_deallocateDirectory;
+ d_deallocateDirectory;
i_popIncomingRequestQueue;
}
transition(M_DWR, PUTX, M_DWRI) {
qw_queueMemoryWBRequest_partialTBE;
c_clearOwner;
- w_deallocateTBE;
i_popIncomingRequestQueue;
}
l_sendWriteBackAck;
da_sendDMAAck;
w_deallocateTBE;
+ d_deallocateDirectory;
l_popMemQueue;
}
c_clearOwner;
v_allocateTBEFromRequestNet;
l_queueMemoryWBRequest;
- d_deallocateDirectory;
i_popIncomingRequestQueue;
}
w_writeDataToMemoryFromTBE;
l_sendWriteBackAck;
w_deallocateTBE;
+ d_deallocateDirectory;
l_popMemQueue;
}
transition(I, PUTX_NotOwner, I) {
b_sendWriteBackNack;
- d_deallocateDirectory;
i_popIncomingRequestQueue;
}
default_param :buffer_size, Integer, 32
# added by SS for TBE
- default_param :number_of_TBEs, Integer, 128
+ default_param :number_of_TBEs, Integer, 256
default_param :recycle_latency, Integer, 10
end