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add roalogic PLIC
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 17 Jun 2018 05:26:29 +0000 (06:26 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 17 Jun 2018 05:26:29 +0000 (06:26 +0100)
shakti/m_class/EINT.mdwn patch | blob | history

diff --git a/shakti/m_class/EINT.mdwn b/shakti/m_class/EINT.mdwn
index 8f7f7c3e818f0fc9f3295f073f063218f2c0ff9b..cb9ce2c8532f5e7d461acf262d8bdd4f4b7eb022 100644 (file)
--- a/shakti/m_class/EINT.mdwn
+++ b/shakti/m_class/EINT.mdwn
@@ -8,3 +8,4 @@ aka "PLIC"
   is a Watchdog Timer and others.
 * <https://opencores.org/project,simple_pic>
 * <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/plic/?at=master>
+* <https://github.com/RoaLogic/plic>
http://libre-riscv.org ikiwiki