targets/sim: generate analyzer.csv

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index df0264eaf4a6ef6dcfa6588c60e37b326a7a013c..7291274fcabb64fdeee16125ff1955c144585ff7 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -174,6 +174,7 @@ def main():
         sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
     if args.with_etherbone:
         sim_config.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.101"})
+
     soc = SimSoC(
         with_sdram=args.with_sdram,
         with_ethernet=args.with_ethernet,
@@ -182,7 +183,10 @@ def main():
         **soc_kwargs)
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
-    builder.build(sim_config=sim_config)
+    vns = builder.build(run=False, sim_config=sim_config)
+    if args.with_analyzer:
+        soc.analyzer.export_csv(vns, "analyzer.csv")
+    builder.build(build=False, sim_config=sim_config)
 
 
 if __name__ == "__main__":

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 07840b826ccd7f79b4211c791b9019691c549177..1e6176eaad74d5f122a635bef18d24c8187216f2 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -145,35 +145,40 @@ def _run_sim(build_name, as_root=False):
 
 class SimVerilatorToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="dut",
-            toolchain_path=None, serial="console", run=True, verbose=True,
+            toolchain_path=None, serial="console", build=True, run=True, verbose=True,
             sim_config=None):
+
         os.makedirs(build_dir, exist_ok=True)
         os.chdir(build_dir)
 
-        if not isinstance(fragment, _Fragment):
-            fragment = fragment.get_fragment()
-        platform.finalize(fragment)
-
-        v_output = platform.get_verilog(fragment, name=build_name)
-        named_sc, named_pc = platform.resolve_signals(v_output.ns)
-        v_output.write(build_name + ".v")
-
-        include_paths = []
-        for source in platform.sources:
-            path = os.path.dirname(source[0]).replace("\\", "\/")
-            if path not in include_paths:
-                include_paths.append(path)
-        include_paths += platform.verilog_include_paths
-        _generate_sim_h(platform)
-        _generate_sim_cpp(platform)
-        _generate_sim_variables(include_paths)
-        if sim_config:
-            _generate_sim_config(sim_config)
-        _build_sim(platform, build_name, verbose)
+        if build:
+            if not isinstance(fragment, _Fragment):
+                fragment = fragment.get_fragment()
+            platform.finalize(fragment)
+
+            v_output = platform.get_verilog(fragment,
+                name=build_name, dummy_signal=False, regular_comb=False, blocking_assign=True)
+            named_sc, named_pc = platform.resolve_signals(v_output.ns)
+            v_output.write(build_name + ".v")
+
+            include_paths = []
+            for source in platform.sources:
+                path = os.path.dirname(source[0]).replace("\\", "\/")
+                if path not in include_paths:
+                    include_paths.append(path)
+            include_paths += platform.verilog_include_paths
+            _generate_sim_h(platform)
+            _generate_sim_cpp(platform)
+            _generate_sim_variables(include_paths)
+            if sim_config:
+                _generate_sim_config(sim_config)
+
+            _build_sim(platform, build_name, verbose)
 
         if run:
             _run_sim(build_name, as_root=sim_config.has_module("ethernet"))
 
-        os.chdir("..")
+        os.chdir("../../")
 
-        return v_output.ns
+        if build:
+            return v_output.ns
\ No newline at end of file