arm: Use zero initialization for the BigRegVect types.

These were being initialized with BigRegVect brv = {0}, which made the
compiler complain because there is internal structure. The first element
of the union is actually an array, and this was telling it to initialize
that array to scalar 0. It was warning about this which was breaking the
build.

Instead, use zero initlization like BigRegVect brv = {}. This
initializes the first element of the union to all zeroes, with all
padding bits initialized to zero as well.

This satisfies the compiler and avoids a build error.

Change-Id: I31e7a8730c538637ff2e0c7fb00a4e12ed05e074
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34575
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index c8f8fcd849cfeaa3d44328ef1ebec358398b8a06..6290203e1812306cc93900503fbfbfe74396d719 100644 (file)
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1452,7 +1452,7 @@ let {{
         rCount = 2
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcReg1, srcReg2;
-        BigRegVect destReg = {0};
+        BigRegVect destReg = {};
         '''
         for reg in range(rCount):
             eWalkCode += '''
@@ -1654,7 +1654,7 @@ let {{
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcReg1;
-        BigRegVect destReg = {0};
+        BigRegVect destReg = {};
         '''
         for reg in range(2):
             eWalkCode += '''
@@ -1884,7 +1884,7 @@ let {{
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcRegs;
-        BigRegVect destReg = {0};
+        BigRegVect destReg = {};
         '''
         for reg in range(rCount):
             eWalkCode += '''
@@ -2010,7 +2010,7 @@ let {{
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
         RegVect srcReg1;
-        BigRegVect destReg = {0};
+        BigRegVect destReg = {};
         '''
         for reg in range(2):
             eWalkCode += '''

diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index 702c128ccf8a54b6ada82696dba7e1febb5dcb64..f049c3ead299bcf2987b255790cfe00cb8e3764e 100644 (file)
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -351,7 +351,7 @@ let {{
         global header_output, exec_output
         eWalkCode = simd64EnabledCheckCode + '''
         RegVect srcReg1;
-        BigRegVect destReg = {0};
+        BigRegVect destReg = {};
         '''
         destReg = 0 if not hi else 2
         for reg in range(2):
@@ -632,7 +632,7 @@ let {{
         global header_output, exec_output
         eWalkCode = simd64EnabledCheckCode + '''
         RegVect srcRegs;
-        BigRegVect destReg = {0};
+        BigRegVect destReg = {};
         '''
         for reg in range(rCount):
             eWalkCode += '''