Fix "make vgtest" so it runs to the end (but now it fails ;)

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
index adef34f5b76613e7e8b4cdfc4c7a0302424c8825..d6e36fb80240ca61991b7210abab7a006e20df05 100644 (file)
--- a/tests/simple/attrib01_module.v
+++ b/tests/simple/attrib01_module.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib01_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib01_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib01_bar bar_instance (clk, rst, inp, out);
 endmodule
 

diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
index 3505e726535ca038f040e38b9ef5f3174ca8e737..989213b773a6fd721c71d864252942c8228dcc03 100644 (file)
--- a/tests/simple/attrib02_port_decl.v
+++ b/tests/simple/attrib02_port_decl.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib02_bar(clk, rst, inp, out);
   (* this_is_clock = 1 *)
   input  wire clk;
   (* this_is_reset = 1 *)
@@ -13,13 +13,13 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib02_foo(clk, rst, inp, out);
   (* this_is_the_master_clock *)
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib02_bar bar_instance (clk, rst, inp, out);
 endmodule
 

diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
index 562d225cd5b87256ba36d2ed2af6c45df6f0f1eb..d2ae989787b095cc520d33dd933d652adb9aa3a4 100644 (file)
--- a/tests/simple/attrib03_parameter.v
+++ b/tests/simple/attrib03_parameter.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib03_bar(clk, rst, inp, out);
 
   (* bus_width *)
   parameter WIDTH = 2;
@@ -17,12 +17,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib03_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp;
   output wire [7:0] out;
 
-  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+  attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
 endmodule
 

diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
index 8b5523406516cb91cfaa95fd49691fa56603ab28..98826e971cbbcbd38a945468b1cc9eecbe4fa37b 100644 (file)
--- a/tests/simple/attrib04_net_var.v
+++ b/tests/simple/attrib04_net_var.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib04_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -21,12 +21,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib04_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib04_bar bar_instance (clk, rst, inp, out);
 endmodule
 

diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
index e20e6631950cda72c348f5d37fe5398b5ecfdf12..8cc471f4e7ce98d09e5edd7ec5027d5dc27eded5 100644 (file)
--- a/tests/simple/attrib05_port_conn.v.DISABLED
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib05_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib05_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+  attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
 endmodule
 

diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
index e21173c58f4e92c995eed7a2b4973cf8af5db715..2bc136f9a294e65f009dd91dff89120006261fe3 100644 (file)
--- a/tests/simple/attrib06_operator_suffix.v
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp_a, inp_b, out);
+module attrib06_bar(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
@@ -11,13 +11,13 @@ module bar(clk, rst, inp_a, inp_b, out);
 
 endmodule
 
-module foo(clk, rst, inp_a, inp_b, out);
+module attrib06_foo(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
   input  wire [7:0] inp_b;
   output wire [7:0] out;
 
-  bar bar_instance (clk, rst, inp_a, inp_b, out);
+  attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out);
 endmodule
 

diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
index f55ef23160919f936b56962da573702d30cc9911..282fc5da7830a4ae9085652290ebaa4335be8f41 100644 (file)
--- a/tests/simple/attrib07_func_call.v.DISABLED
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -1,4 +1,4 @@
-function [7:0] do_add;
+function [7:0] attrib07_do_add;
   input [7:0] inp_a;
   input [7:0] inp_b;
 
@@ -6,7 +6,7 @@ function [7:0] do_add;
 
 endfunction
 
-module foo(clk, rst, inp_a, inp_b, out);
+module attri07_foo(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
@@ -15,7 +15,7 @@ module foo(clk, rst, inp_a, inp_b, out);
 
   always @(posedge clk)
     if (rst) out <= 0;
-    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+    else     out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b);
 
 endmodule
 

diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
index c5a32234eed0663509288ee650bdfee959829e2f..759e67c7bb020978e59529a4dd288cb7afd23699 100644 (file)
--- a/tests/simple/attrib08_mod_inst.v
+++ b/tests/simple/attrib08_mod_inst.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib08_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,13 +10,13 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib08_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
   (* my_module_instance = 99 *)
-  bar bar_instance (clk, rst, inp, out);
+  attrib08_bar bar_instance (clk, rst, inp, out);
 endmodule
 

diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
index 8551bf9d0a482e79583d7f282009d94739296f8f..a72b81ddab4c36ac4776265bb486c0c038f86170 100644 (file)
--- a/tests/simple/attrib09_case.v
+++ b/tests/simple/attrib09_case.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib09_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [1:0] inp;
@@ -15,12 +15,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib09_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [1:0] inp;
   output wire [1:0] out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib09_bar bar_instance (clk, rst, inp, out);
 endmodule
 

diff --git a/tests/simple/case_expr_const.v b/tests/simple/case_expr_const.v
index 58267b965e8c448db0573cab588148b22cd3dc3b..d9169c084c422b4af6375020a4241e9dec3ceeaa 100644 (file)
--- a/tests/simple/case_expr_const.v
+++ b/tests/simple/case_expr_const.v
@@ -1,6 +1,6 @@
 // Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
 // the constant and non-constant case evaluation logic is covered
-module top(
+module case_expr_const_top(
        // expected to output all 1s
     output reg a, b, c, d, e, f, g, h
 );

diff --git a/tests/simple/case_expr_non_const.v b/tests/simple/case_expr_non_const.v
index 7856e781c27138fe2199a6f942e386f0cf55d3dd..6dfc2e54eff5736e8912f0264bd5a3fd657268df 100644 (file)
--- a/tests/simple/case_expr_non_const.v
+++ b/tests/simple/case_expr_non_const.v
@@ -1,6 +1,6 @@
 // Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
 // the constant and non-constant case evaluation logic is covered
-module top(
+module case_expr_non_const_top(
        // expected to output all 1s
     output reg a, b, c, d, e, f, g, h
 );

diff --git a/tests/simple/case_large.v b/tests/simple/case_large.v
index a96ce86fe4e84f9c09bedb50659d640bf449ed61..ec8ed6038685a2db585de803477247fba12f060a 100644 (file)
--- a/tests/simple/case_large.v
+++ b/tests/simple/case_large.v
@@ -1,4 +1,4 @@
-module top (
+module case_lage_top (
     input wire [127:0] x,
     output reg [31:0] y
 );

diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v
index f585be87a97c59c49255b20ece335545b6c7f58d..7e365eeb411e9c37a4a736db2fadb33531f7a35e 100644 (file)
--- a/tests/simple/const_branch_finish.v
+++ b/tests/simple/const_branch_finish.v
@@ -4,7 +4,7 @@
                $finish; \
        end
 
-module top;
+module case_branch_finish_top;
        parameter WIDTH = 32;
        integer j;
        initial begin

diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v
index ee2f12e0689e886697b6b2394a670248ed045bf9..b3f476ce3fc94ab5d6b7f998cf0ee4ac3654331c 100644 (file)
--- a/tests/simple/const_fold_func.v
+++ b/tests/simple/const_fold_func.v
@@ -1,4 +1,4 @@
-module top(
+module const_fold_func_top(
        input wire [3:0] inp,
        output wire [3:0] out1, out2, out3, out4, out5,
        output reg [3:0] out6

diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v
index ca63606d95db3d16f323a94e7772059f999b91aa..fb4f148f6e23245835b7738672bd402d46b7bde1 100644 (file)
--- a/tests/simple/const_func_shadow.v
+++ b/tests/simple/const_func_shadow.v
@@ -1,4 +1,4 @@
-module top(w, x, y, z);
+module const_func_shadow_top(w, x, y, z);
        function [11:0] func;
                input reg [2:0] x;
                input reg [2:0] y;

diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv
index b0a087ecbf07ec1755ab0f82847eac9e62944450..77d7ba26be55fdf3a82c048e4f43147c677ffe11 100644 (file)
--- a/tests/simple/defvalue.sv
+++ b/tests/simple/defvalue.sv
@@ -1,4 +1,4 @@
-module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
+module defvalue_top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
        cnt #(1) foo (.clock, .cnt(cnt1), .delta);
        cnt #(2) bar (.clock, .cnt(cnt2));
 endmodule

diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v
index be759d1a95ebaab1a4da5bb0b5a3595f61064761..0ac7ca3bf522ecbf62a57ea7a71f558d869087e9 100644 (file)
--- a/tests/simple/func_block.v
+++ b/tests/simple/func_block.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module top(inp, out1, out2, out3);
+module func_block_top(inp, out1, out2, out3);
        input wire [31:0] inp;
 
        function automatic [31:0] func1;

diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v
index d61c8cc06fc36a9e686d14dd1aec2cf2625c5593..02cfbcddf55b3bb4a3ce770e693d2dc3233da8f6 100644 (file)
--- a/tests/simple/func_recurse.v
+++ b/tests/simple/func_recurse.v
@@ -1,4 +1,4 @@
-module top(
+module func_recurse_top(
        input wire [3:0] inp,
        output wire [3:0] out1, out2
 );

diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v
index ce81e894e968d6360924233d213aef79eea94aa8..2f82988ae1d4d432f0dbb1c969fb785a4139b7cd 100644 (file)
--- a/tests/simple/func_width_scope.v
+++ b/tests/simple/func_width_scope.v
@@ -1,4 +1,4 @@
-module top(inp, out1, out2);
+module func_width_scope_top(inp, out1, out2);
        input wire signed inp;
 
        localparam WIDTH_A = 5;

diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v
index f42dd2cfc7bf8a18182ff6a6afd539d898a3155c..118c0b008fb9a65c4a0dd0a58517b12413cce4c9 100644 (file)
--- a/tests/simple/genblk_collide.v
+++ b/tests/simple/genblk_collide.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module top1;
+module genblock_collide_top1;
        generate
                if (1) begin : foo
                        if (1) begin : bar
@@ -12,7 +12,7 @@ module top1;
        endgenerate
 endmodule
 
-module top2;
+module genblock_collide_top2;
        genvar i;
        generate
                if (1) begin : foo

diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v
index 98d0e1f4bf6b9a7eb3ea7eb10727c46b8403c917..ca0c0d4a1d3a1822b97ce51e148955f1adbf1c48 100644 (file)
--- a/tests/simple/genblk_dive.v
+++ b/tests/simple/genblk_dive.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top(output wire x);
+module genblk_dive_top(output wire x);
        generate
                if (1) begin : Z
                        if (1) begin : A

diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v
index 7c3a7a756fe4ee500a771806b862509165322fdd..c80c1ac1ac0121bbaa936191d825b4a3fa0e1c3e 100644 (file)
--- a/tests/simple/genblk_order.v
+++ b/tests/simple/genblk_order.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top(
+module genblk_order_top(
        output wire out1,
        output wire out2
 );

diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v
index a04631a209f69e1c8e18fb17e2c81321746e1804..c1348632c2a1003e7895aaafb46f7de35c205c3d 100644 (file)
--- a/tests/simple/genblk_port_shadow.v
+++ b/tests/simple/genblk_port_shadow.v
@@ -1,4 +1,4 @@
-module top(x);
+module genblock_port_shadow_top(x);
        generate
                if (1) begin : blk
                        wire x;

diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 123afaeab9c3639c4658bdfb212749a844419a74..b03044fde0f6d4d23c47d1980b28ca5075282ae9 100644 (file)
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -1,6 +1,6 @@
 
 (* top *)
-module top(a, b, y1, y2, y3, y4);
+module hierarchy_top(a, b, y1, y2, y3, y4);
 input [3:0] a;
 input signed [3:0] b;
 output [7:0] y1, y2, y3, y4;

diff --git a/tests/simple/ifdef_1.v b/tests/simple/ifdef_1.v
index fa962355cb9d092f50df8f4c76b9e83506c1dd4e..f1358185c498b411357e1a065074fed2ae4f659c 100644 (file)
--- a/tests/simple/ifdef_1.v
+++ b/tests/simple/ifdef_1.v
@@ -1,4 +1,4 @@
-module top(o1, o2, o3, o4);
+module ifdef_1_top(o1, o2, o3, o4);
 
 `define FAIL input wire not_a_port;
 

diff --git a/tests/simple/ifdef_2.v b/tests/simple/ifdef_2.v
index 6dd89efed760e22559277503849c53487238e312..9fae7570d3497418294207f315a1ec4fdcfdeb5e 100644 (file)
--- a/tests/simple/ifdef_2.v
+++ b/tests/simple/ifdef_2.v
@@ -1,4 +1,4 @@
-module top(o1, o2, o3);
+module ifdef_2_top(o1, o2, o3);
 
 output wire o1;
 

diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv
index 46b4e5c229fa4e6d92ce375291b086189990c189..42860e21856990f0a88d2b39aaf87e4f0b1a5a22 100644 (file)
--- a/tests/simple/local_loop_var.sv
+++ b/tests/simple/local_loop_var.sv
@@ -1,4 +1,4 @@
-module top(out);
+module local_loop_top(out);
        output integer out;
        initial begin
                integer i;

diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v
index 7ee28ed7013704e306296ac29e93b5ead50f03ef..0cfa005477cf0fb50331d1f02791c746ded73e6e 100644 (file)
--- a/tests/simple/loop_prefix_case.v
+++ b/tests/simple/loop_prefix_case.v
@@ -1,4 +1,4 @@
-module top(
+module loop_prefix_case_top(
        input wire x,
        output reg y
 );

diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v
index 0222a4493d4139573d8ca6e1b551cb1d75550bdf..b75a15ab06c4dd2f85c4b93dc28f6bcb8046d788 100644 (file)
--- a/tests/simple/loop_var_shadow.v
+++ b/tests/simple/loop_var_shadow.v
@@ -1,4 +1,4 @@
-module top(out);
+module loop_var_shadow_top(out);
        genvar i;
        generate
                for (i = 0; i < 2; i = i + 1) begin : loop

diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
index 75c4cd1369f5dbe00ba7d8f2e5827301961243f6..5fc9e288189e31ff064528a415702fcb30154101 100644 (file)
--- a/tests/simple/macro_arg_spaces.sv
+++ b/tests/simple/macro_arg_spaces.sv
@@ -1,4 +1,4 @@
-module top(
+module macro_arg_spaces_top(
        input wire [31:0] i,
        output wire [31:0] x, y, z
 );

diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v
index 3dbb5ea015d61987bb4cb72353bea7a7cce036e1..e0239c08bd48c1c954aabfa017090c8907e1f682 100644 (file)
--- a/tests/simple/macro_arg_surrounding_spaces.v
+++ b/tests/simple/macro_arg_surrounding_spaces.v
@@ -1,4 +1,4 @@
-module top(
+module macr_arg_surrounding_spaces_top(
        IDENT_V_,
        IDENT_W_,
        IDENT_X_,

diff --git a/tests/simple/matching_end_labels.sv b/tests/simple/matching_end_labels.sv
index 09182ebcf4fd54c1dcf644a96acadf2ebafabdbe..2d42e7e10d614b0f9e544c57845f8dd5061317b7 100644 (file)
--- a/tests/simple/matching_end_labels.sv
+++ b/tests/simple/matching_end_labels.sv
@@ -1,4 +1,4 @@
-module top(
+module matching_end_labels_top(
     output reg [7:0]
     out1, out2, out3, out4
 );

diff --git a/tests/simple/mem2reg_bounds_tern.v b/tests/simple/mem2reg_bounds_tern.v
index 89d6dd3e88a1342f69adfaf8b995172f26848095..0e6852fe764a1f8af94a82d128338191dce27b0d 100644 (file)
--- a/tests/simple/mem2reg_bounds_tern.v
+++ b/tests/simple/mem2reg_bounds_tern.v
@@ -1,4 +1,4 @@
-module top(
+module mem2reg_bounds_term_top(
     input clk,
     input wire [1:0] sel,
     input wire [7:0] base,

diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v
index 3e46b72ef1fd85985f2f1a1a20374456d81c91f4..d0778391292f26c578c82b01b84841126f51fe78 100644 (file)
--- a/tests/simple/module_scope.v
+++ b/tests/simple/module_scope.v
@@ -1,29 +1,29 @@
 `default_nettype none
 
-module Example(o1, o2);
+module module_scope_Example(o1, o2);
    parameter [31:0] v1 = 10;
    parameter [31:0] v2 = 20;
    output [31:0] o1, o2;
-   assign Example.o1 = Example.v1;
-   assign Example.o2 = Example.v2;
+   assign module_scope_Example.o1 = module_scope_Example.v1;
+   assign module_scope_Example.o2 = module_scope_Example.v2;
 endmodule
 
-module ExampleLong(o1, o2);
+module module_scope_ExampleLong(o1, o2);
    parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
    parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
    output [31:0] o1, o2;
-   assign ExampleLong.o1 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
-   assign ExampleLong.o2 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
+   assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
+   assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
 endmodule
 
-module top(
+module module_scope_top(
    output [31:0] a1, a2, b1, b2, c1, c2,
    output [31:0] d1, d2, e1, e2, f1, f2
 );
-   Example a(a1, a2);
-   Example #(1) b(b1, b2);
-   Example #(1, 2) c(c1, c2);
-   ExampleLong d(d1, d2);
-   ExampleLong #(1) e(e1, e2);
-   ExampleLong #(1, 2) f(f1, f2);
+   module_scope_Example a(a1, a2);
+   module_scope_Example #(1) b(b1, b2);
+   module_scope_Example #(1, 2) c(c1, c2);
+   module_scope_ExampleLong d(d1, d2);
+   module_scope_ExampleLong #(1) e(e1, e2);
+   module_scope_ExampleLong #(1, 2) f(f1, f2);
 endmodule

diff --git a/tests/simple/module_scope_case.v b/tests/simple/module_scope_case.v
index 1472b6912a2298f1c04df17d01144cb6c1bf7309..bceba4424e169ea3b377d43a1cacea92eb0bd516 100644 (file)
--- a/tests/simple/module_scope_case.v
+++ b/tests/simple/module_scope_case.v
@@ -1,11 +1,11 @@
-module top(
+module module_scope_case_top(
        input wire x,
        output reg y
 );
        always @* begin
-               case (top.x)
-                       1: top.y = 0;
-                       0: top.y = 1;
+               case (module_scope_case_top.x)
+                       1: module_scope_case_top.y = 0;
+                       0: module_scope_case_top.y = 1;
                endcase
        end
 endmodule

diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v
index b8300fc4dc505d65bdc678669642339881511f66..b98b7c8ceed295fa9562177e504b457c100d4e5c 100644 (file)
--- a/tests/simple/named_genblk.v
+++ b/tests/simple/named_genblk.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top;
+module named_genblk_top;
        generate
                if (1) begin
                        wire t;

diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v
index da5593f8a792bb7db2454021a9eb1ab36dd3ca34..70bbc611ba8915bb11d8756e79fd545c8c5eb780 100644 (file)
--- a/tests/simple/nested_genblk_resolve.v
+++ b/tests/simple/nested_genblk_resolve.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top;
+module nested_genblk_resolve_top;
     generate
         if (1) begin
             wire x;

diff --git a/tests/simple/string_format.v b/tests/simple/string_format.v
index ce45ca1e95c41f16ee0acc58c0a2e43b98590c9c..cb7b419ac279457d492880b8c405c410fad9552b 100644 (file)
--- a/tests/simple/string_format.v
+++ b/tests/simple/string_format.v
@@ -1,4 +1,4 @@
-module top;
+module string_format_top;
        parameter STR = "something interesting";
        initial begin
                $display("A: %s", STR);

diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv
index e81b457a88a819d005069e075c281be8f472298c..e78c577daae374eb64e38de85b72c249481cdd83 100644 (file)
--- a/tests/simple/unnamed_block_decl.sv
+++ b/tests/simple/unnamed_block_decl.sv
@@ -1,4 +1,4 @@
-module top(z);
+module unnamed_block_decl(z);
        output integer z;
        initial begin
                integer x;

diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v
index 34404aa26b2f39c928dac2c6c2ecc2dfb44a4cdf..40502acfc017b65382848c355120d6cbfa7c2c09 100644 (file)
--- a/tests/simple/wandwor.v
+++ b/tests/simple/wandwor.v
@@ -5,9 +5,9 @@ module wandwor_test0 (A, B, C, D, X, Y, Z);
        output Z;
 
        assign X = A, X = B, Y = C, Y = D;
-       foo foo_0 (C, D, X);
-       foo foo_1 (A, B, Y);
-       foo foo_2 (X, Y, Z);
+       wandwor_foo foo_0 (C, D, X);
+       wandwor_foo foo_1 (A, B, Y);
+       wandwor_foo foo_2 (X, Y, Z);
 endmodule
 
 module wandwor_test1 (A, B, C, D, X, Y, Z);
@@ -16,7 +16,7 @@ module wandwor_test1 (A, B, C, D, X, Y, Z);
        output wand [3:0] Y;
        output Z;
 
-       bar bar_inst (
+       wandwor_bar bar_inst (
                .I0({A, B}),
                .I1({B, A}),
                .O({X, Y})
@@ -27,10 +27,10 @@ module wandwor_test1 (A, B, C, D, X, Y, Z);
        assign Z = ^{X,Y};
 endmodule
 
-module foo(input I0, I1, output O);
+module wandwor_foo(input I0, I1, output O);
        assign O = I0 ^ I1;
 endmodule
 
-module bar(input [7:0] I0, I1, output [7:0] O);
+module wandwor_bar(input [7:0] I0, I1, output [7:0] O);
        assign O = I0 + I1;
 endmodule