opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers

Currently, the get_disassembler() implementations for riscv, csky, and
rl78--and mep_print_insn() for mep--access ELF variants of union fields
without first checking that the bfd actually represents an ELF.  This
causes undefined behavior and crashes when disassembling non-ELF files
(the "binary" BFD, for example).  Fix that.

diff --git a/cpu/mep.opc b/cpu/mep.opc
index 6ad0c5879e810ae0afef3f2ae11597b3cd0bea08..278b4454c336a6022dd09145c858c7e5b8fbfa43 100644 (file)
--- a/cpu/mep.opc
+++ b/cpu/mep.opc
@@ -1451,12 +1451,15 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   if (info->section && info->section->owner)
     {
       bfd *abfd = info->section->owner;
-      mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
-      /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
+      if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
+       {
+         mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
+         /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
 
-      cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
-      if (cop_type == EF_MEP_COP_IVC2)
-       ivc2 = 1;
+         cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
+         if (cop_type == EF_MEP_COP_IVC2)
+           ivc2 = 1;
+       }
     }
 
   /* Picking the right ISA bitmask for the current context is tricky.  */

diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c
index 96163166fc38a4aab301acdc85715282149e4940..b7c833623e5cbec9e097dfd43d77374906da5e2e 100644 (file)
--- a/opcodes/csky-dis.c
+++ b/opcodes/csky-dis.c
@@ -239,7 +239,7 @@ csky_get_disassembler (bfd *abfd)
 {
   obj_attribute *attr;
   const char *sec_name = NULL;
-  if (!abfd)
+  if (!abfd || bfd_get_flavour (abfd) != bfd_target_elf_flavour)
     dis_info.isa = CSKY_DEFAULT_ISA;
   else
     {

diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index 188ee29820291defdefaef96c70c7d0cf8f4be2b..c56e90dcc6f53edbc481eeb38809d48e2911b37f 100644 (file)
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -647,12 +647,15 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   if (info->section && info->section->owner)
     {
       bfd *abfd = info->section->owner;
-      mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
-      /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
+      if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
+       {
+         mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
+         /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
 
-      cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
-      if (cop_type == EF_MEP_COP_IVC2)
-       ivc2 = 1;
+         cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
+         if (cop_type == EF_MEP_COP_IVC2)
+           ivc2 = 1;
+       }
     }
 
   /* Picking the right ISA bitmask for the current context is tricky.  */

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index bfaefa3fb475f04fdcbddba67bb3b978a6e01bd7..9ff3116777569f39b56e92f4a3af9ec44f56efda 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1002,24 +1002,20 @@ riscv_get_disassembler (bfd *abfd)
 {
   const char *default_arch = "rv64gc";
 
-  if (abfd)
+  if (abfd && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
     {
-      const struct elf_backend_data *ebd = get_elf_backend_data (abfd);
-      if (ebd)
+      const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
+      if (bfd_get_section_by_name (abfd, sec_name) != NULL)
        {
-         const char *sec_name = ebd->obj_attrs_section;
-         if (bfd_get_section_by_name (abfd, sec_name) != NULL)
-           {
-             obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
-             unsigned int Tag_a = Tag_RISCV_priv_spec;
-             unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
-             unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
-             riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
-                                                     attr[Tag_b].i,
-                                                     attr[Tag_c].i,
-                                                     &default_priv_spec);
-             default_arch = attr[Tag_RISCV_arch].s;
-           }
+         obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
+         unsigned int Tag_a = Tag_RISCV_priv_spec;
+         unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
+         unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
+         riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
+                                                 attr[Tag_b].i,
+                                                 attr[Tag_c].i,
+                                                 &default_priv_spec);
+         default_arch = attr[Tag_RISCV_arch].s;
        }
     }
 

diff --git a/opcodes/rl78-dis.c b/opcodes/rl78-dis.c
index cc08a298688a8d70ebcf2ca8c8af4228e1d6fedf..2d7ffb26eba48ec506a7425f6097af334fd2fd0e 100644 (file)
--- a/opcodes/rl78-dis.c
+++ b/opcodes/rl78-dis.c
@@ -408,7 +408,7 @@ rl78_get_disassembler (bfd *abfd)
 {
   int cpu = E_FLAG_RL78_ANY_CPU;
 
-  if (abfd != NULL)
+  if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
     cpu = abfd->tdata.elf_obj_data->elf_header->e_flags & E_FLAG_RL78_CPU_MASK;
 
   switch (cpu)