Bit-vector operator bvxnor was previously mistakenly marked as
left-assoicative in SMT-LIB. This has recently been corrected in
SMT-LIB. We now restrict bvxnor to only allow two operands in order to
avoid confusion about the semantics, since the behavior of n-ary
operands to bvxnor is now undefined in SMT-LIB.
SMT-LIB 2.6 semantics.
* The `competition` build type includes the dependencies used for SMT-COMP by
default. Note that this makes this build type produce GPL-licensed binaries.
+* Bit-vector operator bvxnor was previously mistakenly marked as
+ left-assoicative in SMT-LIB. This has recently been corrected in SMT-LIB. We
+ now restrict bvxnor to only allow two operands in order to avoid confusion
+ about the semantics, since the behavior of n-ary operands to bvxnor is now
+ undefined in SMT-LIB.
Changes since 1.7
if (echildren.size() > 2)
{
if (kind == INTS_DIVISION || kind == XOR || kind == MINUS
- || kind == DIVISION || kind == BITVECTOR_XNOR || kind == HO_APPLY)
+ || kind == DIVISION || kind == HO_APPLY)
{
// left-associative, but CVC4 internally only supports 2 args
res = d_exprMgr->mkLeftAssociative(k, echildren);
(not (= (bvmul x y z) (bvmul (bvmul x y) z)))
(not (= (bvand x y z) (bvand (bvand x y) z)))
(not (= (bvor x y z) (bvor (bvor x y) z)))
- (not (= (bvxor x y z) (bvxor (bvxor x y) z)))
- (not (= (bvxnor x y z) (bvxnor (bvxnor x y) z)))))
+ (not (= (bvxor x y z) (bvxor (bvxor x y) z)))))
(check-sat)