Set tval to 0 on traps with no specified tval

Simply not writing the register was not a conformant implementation.

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 722ca45292abe5011e441adf5c2b1fa9e2b32921..564b34f286ee3ce1120006a684a28ba6ebfbdaa4 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -272,8 +272,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     state.pc = state.stvec;
     state.scause = t.cause();
     state.sepc = epc;
-    if (t.has_badaddr())
-      state.sbadaddr = t.get_badaddr();
+    state.sbadaddr = t.get_badaddr();
 
     reg_t s = state.mstatus;
     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
@@ -286,8 +285,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     state.pc = (state.mtvec & ~(reg_t)1) + vector;
     state.mepc = epc;
     state.mcause = t.cause();
-    if (t.has_badaddr())
-      state.mbadaddr = t.get_badaddr();
+    state.mbadaddr = t.get_badaddr();
 
     reg_t s = state.mstatus;
     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));

diff --git a/riscv/trap.h b/riscv/trap.h
index 91e522396b42d9887372897ed19fe30252672c4a..1fe44eb08d6aea33aab49d631fc8c167a5a6f4cb 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -14,7 +14,7 @@ class trap_t
   trap_t(reg_t which) : which(which) {}
   virtual const char* name();
   virtual bool has_badaddr() { return false; }
-  virtual reg_t get_badaddr() { abort(); }
+  virtual reg_t get_badaddr() { return 0; }
   reg_t cause() { return which; }
  private:
   char _name[16];