+2016-07-22 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
+ comments to explain why certain error messages make mention of
+ undocumented options.
+ (rs6000_invalid_builtin): Change error messages to replace mention
+ of undocumented options with mention of the -mcpu=power9 option
+ that enables those undocumented options.
+ * config/rs6000/rs6000.h (MASK_FLOAT128): New macro.
+ (RS6000_BTM_FLOAT128): Use the new MASK_FLOAT128 macro in the
+ definition of this macro to correct an existing error.
+ * config/rs6000/rs6000.opt: Add the Undocumented qualifier to the
+ mpower9-fusion, mpower9-vector, mpower9-dform, and mmodulo entries.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions): Modify
+ descriptions of built-in functions so that they depend on
+ -mcpu=power9 instead of on the corresponding undocumented flags.
+ * doc/invoke.texi (Option Summary): Remove all mention of newly
+ undocumented flags.
+ (IBM RS/6000 and PowerPC Options): Likewise.
+ * doc/md.texi (Constraints for Particuliar Machines): Remove all
+ mention of newly undocumented flags.
+
2016-07-22 Evgeny Stupachenko <evstupac@gmail.com>
* ipa-cp.c (determine_versionability): Do not create constprop clones,
{
if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-fusion without selecting power8-fusion, they
+ already know about undocumented flags. */
error ("-mpower9-fusion requires -mpower8-fusion");
rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
}
/* ISA 3.0 vector instructions include ISA 2.07. */
if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-vector without selecting power8-vector, they
+ already know about undocumented flags. */
if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
error ("-mpower9-vector requires -mpower8-vector");
rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
/* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR) && !TARGET_P9_VECTOR)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-dform without selecting power9-vector, they
+ already know about undocumented flags. */
if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
error ("-mpower9-dform requires -mpower9-vector");
rs6000_isa_flags &= ~(OPTION_MASK_P9_DFORM_SCALAR
if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-dform without selecting upper-regs-df, they
+ already know about undocumented flags. */
if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
error ("-mpower9-dform requires -mupper-regs-df");
rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
error ("Builtin function %s requires the -mpower8-vector option", name);
else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
- error ("Builtin function %s requires the -mpower9-vector option", name);
+ error ("Builtin function %s requires the -mcpu=power9 option", name);
else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
== (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
- error ("Builtin function %s requires the -mpower9-misc and"
+ error ("Builtin function %s requires the -mcpu=power9 and"
" -m64 options", name);
else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
- error ("Builtin function %s requires the -mpower9-misc option", name);
+ error ("Builtin function %s requires the -mcpu=power9 option", name);
else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
== (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
error ("Builtin function %s requires the -mhard-float and"
#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
#define MASK_DLMZB OPTION_MASK_DLMZB
#define MASK_EABI OPTION_MASK_EABI
+#define MASK_FLOAT128 OPTION_MASK_FLOAT128
#define MASK_FPRND OPTION_MASK_FPRND
#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
-#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */
+#define RS6000_BTM_FLOAT128 MASK_FLOAT128 /* IEEE 128-bit float. */
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
| RS6000_BTM_VSX \
Analyze and remove doubleword swaps from VSX computations.
mpower9-fusion
-Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
+Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
Fuse certain operations together for better performance on power9.
mpower9-misc
Use/do not use certain scalar instructions added in ISA 3.0.
mpower9-vector
-Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
+Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use/do not use vector instructions added in ISA 3.0.
mpower9-dform-scalar
Use/do not use vector register+offset memory instructions added in ISA 3.0.
mpower9-dform
-Target Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
+Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
Use/do not use register+offset memory instructions added in ISA 3.0.
mpower9-minmax
Fuse medium/large code model toc references with the memory instruction.
mmodulo
-Target Report Mask(MODULO) Var(rs6000_isa_flags)
+Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
Generate the integer modulo instructions.
mfloat128
int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t);
@end smallexample
-If the ISA 3.0 additions to the vector/scalar (power9-vector)
-instruction set are available:
+If the ISA 3.0 instruction set additions (@option{-mcpu=power9})
+are available:
@smallexample
vector long long vec_vctz (vector long long);
vector unsigned long long vec_vprtybd (vector unsigned long long);
@end smallexample
-
-If the ISA 3.0 additions to the vector/scalar (power9-vector)
-instruction set are available for 64-bit targets:
+On 64-bit targets, if the ISA 3.0 additions (@option{-mcpu=power9})
+are available:
@smallexample
vector long vec_vprtyb (vector long);
@end smallexample
The following built-in vector functions are available for the PowerPC family
-of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
-or with @option{-mpower9-vector}:
+of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
@smallexample
__vector unsigned char
vec_slv (__vector unsigned char src, __vector unsigned char shift_distance);
with this resulting value coerced to the @code{unsigned char} type.
The following built-in functions are available for the PowerPC family
-of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
-or with @option{-mpower9-vector}:
+of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
@smallexample
__vector unsigned char
vec_absd (__vector unsigned char arg1, __vector unsigned char arg2);
integer that is 0 or 1. The third argument to these builtin functions
must be a constant integer in the range of 0 to 15.
-If the ISA 3.0 additions to the vector/scalar (power9-vector)
-instruction set are available, the following additional functions are
-available for both 32-bit and 64-bit targets.
+If the ISA 3.0 instruction set additions
+are enabled (@option{-mcpu=power9}), the following additional
+functions are available for both 32-bit and 64-bit targets.
vector short vec_xl (int, vector short *);
vector short vec_xl (int, short *);
-mcompat-align-parm -mno-compat-align-parm @gol
-mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
-mupper-regs-di -mno-upper-regs-di @gol
--mupper-regs -mno-upper-regs -mmodulo -mno-modulo @gol
+-mupper-regs -mno-upper-regs @gol
-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
--mpower9-fusion -mno-mpower9-fusion -mpower9-vector -mno-power9-vector @gol
--mpower9-dform -mno-power9-dform -mlra -mno-lra}
+-mlra -mno-lra}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
-mcrypto -mdirect-move -mhtm -mpower8-fusion -mpower8-vector @gol
--mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
--mpower9-fusion -mpower9-vector -mpower9-dform}
+-mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware}
The particular options set for any particular CPU varies between
compiler versions, depending on what setting seems to produce optimal
floating point register set that were added in version 2.07 of the
PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or
-@option{-mpower9} options.
+@option{-mcpu=power9} options.
@item -mupper-regs
@itemx -mno-upper-regs
not use either @option{-mfloat128} or @option{-mfloat128-hardware},
the IEEE 128-bit floating point support will not be enabled.
-@item -mmodulo
-@itemx -mno-modulo
-@opindex mmodulo
-@opindex mno-module
-Generate code that uses (does not use) the ISA 3.0 integer modulo
-instructions. The @option{-mmodulo} option is enabled by default
-with the @option{-mcpu=power9} option.
-
-@item -mpower9-fusion
-@itemx -mno-power9-fusion
-@opindex mpower9-fusion
-@opindex mno-power9-fusion
-Generate code that keeps (does not keeps) some operations adjacent so
-that the instructions can be fused together on power9 and later
-processors.
-
-@item -mpower9-vector
-@itemx -mno-power9-vector
-@opindex mpower9-vector
-@opindex mno-power9-vector
-Generate code that uses (does not use) the vector and scalar
-instructions that were added in version 3.0 of the PowerPC ISA. Also
-enable the use of built-in functions that allow more direct access to
-the vector instructions.
-
-@item -mpower9-dform
-@itemx -mno-power9-dform
-@opindex mpower9-dform
-@opindex mno-power9-dform
-Enable (disable) scalar d-form (register + offset) memory instructions
-to load/store traditional Altivec registers. If the @var{LRA} register
-allocator is enabled, also enable (disable) vector d-form memory
-instructions.
-
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs
is incorrect.
@item wb
-Altivec register if @option{-mpower9-dform} is used or NO_REGS.
+Altivec register if @option{-mcpu=power9} is used or NO_REGS.
@item wd
VSX vector register to hold vector double data or NO_REGS.
@item we
-VSX register if the @option{-mpower9-vector} and @option{-m64} options
+VSX register if the @option{-mcpu=power9} and @option{-m64} options
were used or NO_REGS.
@item wf
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