add verilator snoop of LDST request address

(to capture requests which go through the MMU. current dump only outputs
physical address: this is the virtual address)

diff --git a/core.vhdl b/core.vhdl
index f5638c899a7bc32c6571c27b595856a564532715..a6cad76573cf4ffa1b34db72fed513e46dc749e3 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -46,7 +46,9 @@ entity core is
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
     msr_o: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
+    insn: out std_ulogic_vector(31 downto 0);
+    ldst_req: out std_ulogic;
+    ldst_addr: out std_ulogic_vector(63 downto 0)
         );
 end core;
 
@@ -446,6 +448,11 @@ begin
     msr_o <= msr;
     insn <= icache_to_decode1.insn;
     nia_req <= icache_to_decode1.valid and fetch1_to_icache.sequential;
+    -- hmmm....
+    ldst_req <= execute1_to_loadstore1.valid;
+    ldst_addr <= std_ulogic_vector(unsigned(execute1_to_loadstore1.addr1) +
+                                   unsigned(execute1_to_loadstore1.addr2))
+                  when execute1_to_loadstore1.valid = '1' else (others => '0');
 
     debug_0: entity work.core_debug
 

diff --git a/core_dummy.vhdl b/core_dummy.vhdl
index 9ceab195b446c1be022d62a448237d9a19bd28f1..8967bb73c3687d493ecd9b9e80ae0a57854c4f38 100644 (file)
--- a/core_dummy.vhdl
+++ b/core_dummy.vhdl
@@ -45,7 +45,10 @@ entity core is
     -- for verilator debugging
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
+    msr_o: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
         );
 end core;
 

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 32bdfcec2f19d7a294d73d31cacbd865494c7d4e..66c65cc2cc34561f9be7c12ca1357a4aad432b1d 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -42,8 +42,9 @@ entity toplevel is
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
     msr_o: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
-
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
        );
 end entity toplevel;
 
@@ -115,7 +116,9 @@ begin
         nia_req           => nia_req,
         nia               => nia,
         msr_o             => msr_o,
-        insn              => insn
+        insn              => insn,
+        ldst_req          => ldst_req,
+        ldst_addr         => ldst_addr
            );
 
 end architecture behaviour;

diff --git a/soc.vhdl b/soc.vhdl
index 22122479059c371132d5312c478522eb7f3913d4..042f224784c9e4739bbef15815aa8b6fcbdf2d15 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -123,7 +123,9 @@ entity soc is
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
     msr_o: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
        );
 end entity soc;
 
@@ -278,7 +280,9 @@ architecture behaviour of soc is
         nia_req: out std_ulogic;
         msr_o: out std_ulogic_vector(63 downto 0);
         nia: out std_ulogic_vector(63 downto 0);
-        insn: out std_ulogic_vector(31 downto 0)
+        insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
         );
     end component;
 begin
@@ -328,7 +332,9 @@ begin
         nia_req           => nia_req,
         nia               => nia,
         msr_o             => msr_o,
-        insn              => insn
+        insn              => insn,
+        ldst_req          => ldst_req,
+        ldst_addr         => ldst_addr
            );
     end generate;
 

diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index b75eb528373caf0f5e542fd88afed57be14bb2af..8ef758dc5e94c24ffc520bbbd6513900f29073bd 100644 (file)
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -197,9 +197,18 @@ int main(int argc, char **argv)
 
 #ifdef BRAM_DEBUG
         if (top->nia_req) {
-            fprintf(dump, "pc %8x insn %8x msr %16lx\n",
+            fprintf(dump, "pc %8x insn %8x msr %16lx",
                                 top->nia, top->insn, top->msr_o);
         }
+        if (top->ldst_req) {
+            if (!top->nia_req) {
+                fprintf(dump, "pc %-8s insn %-8s msr %-16s", "", "", "");
+            }
+            fprintf(dump, "    ldst %16lx", top->ldst_addr);
+        }
+        if (top->ldst_req || top->nia_req) {
+            fprintf(dump, "\n");
+        }
         if (top->bram_we) {
             fprintf(dump, "                          " \
                           "wr @ %08x do %16lx sel %02x ",