}
if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
have_face = TRUE;
- if (rctx->sprite_coord_enable & (1 << i)) {
+ if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
+ rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
tmp |= S_028644_PT_SPRITE_TEX(1);
}
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
}
if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
have_face = TRUE;
- if (rctx->sprite_coord_enable & (1 << i)) {
+ if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
+ rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
tmp |= S_028644_PT_SPRITE_TEX(1);
}
r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
offset -= ctx->groups[EVERGREEN_GROUP_RESOURCE].start_offset;
id = ctx->groups[EVERGREEN_GROUP_RESOURCE].offset_block_id[offset >> 2];
block = &ctx->groups[EVERGREEN_GROUP_RESOURCE].blocks[id];
+ if (state == NULL) {
+ block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+ radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+ return;
+ }
block->reg[0] = state->regs[0].value;
block->reg[1] = state->regs[1].value;
block->reg[2] = state->regs[2].value;
offset -= ctx->groups[EVERGREEN_GROUP_SAMPLER].start_offset;
id = ctx->groups[EVERGREEN_GROUP_SAMPLER].offset_block_id[offset >> 2];
block = &ctx->groups[EVERGREEN_GROUP_SAMPLER].blocks[id];
+ if (state == NULL) {
+ block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+ return;
+ }
block->reg[0] = state->regs[0].value;
block->reg[1] = state->regs[1].value;
block->reg[2] = state->regs[2].value;
fake_offset -= ctx->groups[EVERGREEN_GROUP_SAMPLER_BORDER].start_offset;
id = ctx->groups[EVERGREEN_GROUP_SAMPLER_BORDER].offset_block_id[fake_offset >> 2];
block = &ctx->groups[EVERGREEN_GROUP_SAMPLER_BORDER].blocks[id];
+ if (state == NULL) {
+ block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+ return;
+ }
+ if (state->nregs <= 3) {
+ return;
+ }
block->reg[0] = id;
block->reg[1] = state->regs[3].value;
block->reg[2] = state->regs[4].value;
offset = 0x0003C000 + id * 0xc;
evergreen_context_pipe_state_set_sampler(ctx, state, offset);
- if (state->nregs > 3) {
- evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
- }
+ evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
}
void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
offset = 0x0003C0D8 + id * 0xc;
evergreen_context_pipe_state_set_sampler(ctx, state, offset);
- if (state->nregs > 3) {
- evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
- }
+ evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
}
offset -= ctx->groups[R600_GROUP_RESOURCE].start_offset;
id = ctx->groups[R600_GROUP_RESOURCE].offset_block_id[offset >> 2];
block = &ctx->groups[R600_GROUP_RESOURCE].blocks[id];
+ if (state == NULL) {
+ block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+ radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+ return;
+ }
block->reg[0] = state->regs[0].value;
block->reg[1] = state->regs[1].value;
block->reg[2] = state->regs[2].value;
offset -= ctx->groups[R600_GROUP_SAMPLER].start_offset;
id = ctx->groups[R600_GROUP_SAMPLER].offset_block_id[offset >> 2];
block = &ctx->groups[R600_GROUP_SAMPLER].blocks[id];
+ if (state == NULL) {
+ block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+ return;
+ }
block->reg[0] = state->regs[0].value;
block->reg[1] = state->regs[1].value;
block->reg[2] = state->regs[2].value;
offset -= ctx->groups[R600_GROUP_CONFIG].start_offset;
id = ctx->groups[R600_GROUP_CONFIG].offset_block_id[offset >> 2];
block = &ctx->groups[R600_GROUP_CONFIG].blocks[id];
+ if (state == NULL) {
+ block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+ return;
+ }
+ if (state->nregs <= 3) {
+ return;
+ }
block->reg[0] = state->regs[3].value;
block->reg[1] = state->regs[4].value;
block->reg[2] = state->regs[5].value;
offset = 0x0003C000 + id * 0xc;
r600_context_pipe_state_set_sampler(ctx, state, offset);
- if (state->nregs > 3) {
- offset = 0x0000A400 + id * 0x10;
- r600_context_pipe_state_set_sampler_border(ctx, state, offset);
- }
+ offset = 0x0000A400 + id * 0x10;
+ r600_context_pipe_state_set_sampler_border(ctx, state, offset);
}
void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
offset = 0x0003C0D8 + id * 0xc;
r600_context_pipe_state_set_sampler(ctx, state, offset);
- if (state->nregs > 3) {
- offset = 0x0000A600 + id * 0x10;
- r600_context_pipe_state_set_sampler_border(ctx, state, offset);
- }
+ offset = 0x0000A600 + id * 0x10;
+ r600_context_pipe_state_set_sampler_border(ctx, state, offset);
}
void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group)