div, fcvt

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index f8b47852ba48c459a5f02b9d7a8f61cc06db4f82..2f172eae2374bb9535f1b0d1f6869706056810aa 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,8 +1,8 @@
 require_extension('M');
 require_rv64;
-sreg_t lhs = sext32(RS1);
-sreg_t rhs = sext32(RS2);
-if(rhs == 0)
+sv_sreg_t lhs = sext32(RS1);
+sv_sreg_t rhs = sext32(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(UINT64_MAX);
 else
   WRITE_RD(sext32(rv_div(lhs, rhs)));

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 4c4861c1555c48c9e136086de2890a568e9ddb2e..76ec6e6eafb0b15f9c7145680ebcaa56f995bcfd 100644 (file)
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1));
+WRITE_FRD(i32_to_f64(sv_reg_int32(RS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 1dbf218a1cfa95a4799bb9606e0d35d3f89c9e7f..afa6d7273d59462cc9a8ff4f188855f28720be4a 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1));
+WRITE_FRD(ui32_to_f64(sv_reg_uint32(RS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_q_w.h b/riscv/insns/fcvt_q_w.h
index fb83f15d99ce0feaef0f8af35077f83f1aef3377..1edd3192f809fb5c5a95fbc67ca1b9f90861709f 100644 (file)
--- a/riscv/insns/fcvt_q_w.h
+++ b/riscv/insns/fcvt_q_w.h
@@ -1,5 +1,5 @@
 require_extension('Q');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f128((int32_t)RS1));
+WRITE_FRD(i32_to_f128(sv_reg_int32(RS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_q_wu.h b/riscv/insns/fcvt_q_wu.h
index 7c2ae97ec8f2acde801788acdc6d7f053abfb226..8ec77b3af1cdf31cb047fca4661c790e4b9eef6d 100644 (file)
--- a/riscv/insns/fcvt_q_wu.h
+++ b/riscv/insns/fcvt_q_wu.h
@@ -1,5 +1,5 @@
 require_extension('Q');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f128((uint32_t)RS1));
+WRITE_FRD(ui32_to_f128(sv_reg_uint32(RS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 1ddabd87c12cda406cc3e924ba9c3103815d8298..92af604ac2821d7edb05305c2f99e10ca663c32b 100644 (file)
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f32((int32_t)RS1));
+WRITE_FRD(i32_to_f32(sv_reg_int32(RS1)));
 set_fp_exceptions;