radeonsi/gfx10: fix and enable CLEAR_STATE
authorMarek Olšák <marek.olsak@amd.com>
Thu, 18 Jul 2019 03:29:22 +0000 (23:29 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Tue, 23 Jul 2019 19:03:47 +0000 (15:03 -0400)
it was a driver bug.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
src/gallium/drivers/radeonsi/si_gfx_cs.c
src/gallium/drivers/radeonsi/si_pipe.c

index 843f8206149566014db6acc8a288112bdc37bb55..1560e3a2df36893be1e73885afa55e624b9e59fc 100644 (file)
@@ -508,6 +508,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG]  = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP]  = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL]  = 0x00000000;
+               ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_NGG_CNTL]  = 0x00000000;
index 65cfe7f4878a62842cf697dbddb72fb3f5c80931..96c71d91bd5621f0244422954850982df92077c7 100644 (file)
@@ -1088,7 +1088,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
         * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
         * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
        sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
-                                  sscreen->info.chip_class <= GFX9 &&
                                   sscreen->info.is_amdgpu;
 
        sscreen->has_distributed_tess =