+2019-07-02 Barnaby Wilks <barnaby.wilks@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Add error check.
+ * testsuite/gas/aarch64/diagnostic.l: New test.
+ * testsuite/gas/aarch64/diagnostic.s: New test.
+ * testsuite/gas/aarch64/illegal.l: New tests.
+ * testsuite/gas/aarch64/illegal.s: New tests.
+
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-movprfx_27.s,
val = parse_vector_reg_list (&str, reg_type, &vectype);
if (val == PARSE_FAIL)
goto failure;
+
if (! reg_list_valid_p (val, /* accept_alternate */ 0))
{
set_fatal_syntax_error (_("invalid register list"));
goto failure;
}
+
+ if (vectype.width != 0 && *str != ',')
+ {
+ set_fatal_syntax_error
+ (_("expected element type rather than vector type"));
+ goto failure;
+ }
+
info->reglist.first_regno = (val >> 2) & 0x1f;
info->reglist.num_regs = (val & 0x3) + 1;
}
[^:]*:311: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x26,\[x3\]'
[^:]*:312: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x26,\[x5\]'
[^:]*:313: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x1,\[x26\]'
+[^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
stlxr w26, x26, [x3]
ldxp x26, x26, [x5]
ldxp x26, x1, [x26]
+ st4 {v0.16b-v3.16b}[4], [x0]
[^:]*:585: Error: .*`fcmgt v0\.2d,v0\.2d,#-0\.0'
[^:]*:589: Error: .*`fmov s9,x0'
[^:]*:590: Error: .*`fmov d7,w1'
-[^:]*:592: Error: .*
+[^:]*:592: Error: .*`st1 {v0\.16b}\[0\],\[x0\]'
+[^:]*:593: Error: .*`st2 {v0\.16b-v1\.16b}\[1\],\[x0\]'
+[^:]*:594: Error: .*`st3 {v0\.16b-v2\.16b}\[2\],\[x0\]'
+[^:]*:595: Error: .*`st4 {v0\.8b-v3\.8b}\[4\],\[x0\]'
+[^:]*:597: Error: .*
fmov s9, x0
fmov d7, w1
+ st1 {v0.16b}[0],[x0]
+ st2 {v0.16b-v1.16b}[1],[x0]
+ st3 {v0.16b-v2.16b}[2],[x0]
+ st4 {v0.8b-v3.8b}[4],[x0]
+
// End (for errors during literal pool generation)