hdl.dsl: gracefully handle FSM with no states.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 5b820895ba550d07b16f3de24e2c987b48bbcaf8..415ad951c9d077c6e7476030df7482a451ea2b95 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -337,6 +337,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         if name == "FSM":
             fsm_signal, fsm_reset, fsm_encoding, fsm_decoding, fsm_states = \
                 data["signal"], data["reset"], data["encoding"], data["decoding"], data["states"]
+            if not fsm_states:
+                return
             fsm_signal.nbits = bits_for(len(fsm_encoding) - 1)
             if fsm_reset is None:
                 fsm_signal.reset = fsm_encoding[next(iter(fsm_states))]

diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 04f7e8ca497f8f3521b700b0bb67bb2a503ad90f..714eb479228c392d96775f472a0ef03b7434fc91 100644 (file)
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -449,6 +449,14 @@ class DSLTestCase(FHDLTestCase):
         )
         """)
 
+    def test_FSM_empty(self):
+        m = Module()
+        with m.FSM():
+            pass
+        self.assertRepr(m._statements, """
+        ()
+        """)
+
     def test_FSM_wrong_redefined(self):
         m = Module()
         with m.FSM():