[0-9a-f]+[048c] <[^>]*> 0524ac02[ \t]+mpy \.M2 5,b9,b10
[0-9a-f]+[048c] <[^>]*> a62f9c02[ \t]+\[a2\] mpy \.M2X -4,a11,b12
[0-9a-f]+[048c] <[^>]*> 02080700[ \t]+mpydp \.M1 a1:a0,a3:a2,a5:a4
+[0-9a-f]+[048c] <[^>]*> 00001702[ \t]+mpydp \.M2X b1:b0,a1:a0,b1:b0
[0-9a-f]+[048c] <[^>]*> 6520c702[ \t]+\[b2\] mpydp \.M2 b7:b6,b9:b8,b11:b10
[0-9a-f]+[048c] <[^>]*> 01040080[ \t]+mpyh \.M1 a0,a1,a2
[0-9a-f]+[048c] <[^>]*> b2907080[ \t]+\[!a2\] mpyh \.M1X a3,b4,a5
#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }
-#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
+#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }
#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }
#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }
ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
ENC(src2, reg, 1), ENC(dst, reg, 2)))
-INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS,
- FIX2(FIX(op, 0x0e), FIX(x, 0)),
- OP3(ORREGD1234, ORREGD1324, OWREGD910),
- ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
- ENC(dst, reg, 2)))
+INSN(mpydp, m, mpy, mpydp, C67X, 0,
+ FIX1(FIX(op, 0x0e)),
+ OP3(ORREGD1234, ORXREGD1324, OWREGD910),
+ ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+ ENC(src2, reg, 1), ENC(dst, reg, 2)))
INSN(mpyh, m, mpy, 1616_m, C62X, 0,
FIX1(FIX(op, 0x01)),
#undef OWDREGD5
#undef ORREGD12
#undef ORXREGD12
-#undef ORREGD1234
+#undef ORXREGD1234
#undef ORREGD1324
#undef OWREGD910
#undef ORCREG1