Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys

Also some minor fixes to the original PR.

diff --cc passes/opt/opt_reduce.cc
index 09f6e12e90cc83f724ba1c50757a4b87026a82a1,8126f3c0dcc90fe1f97276624bfbb48747d1d3e3..f74655d1ced393734b3626769aa51abcdb0addaf
--- 1/passes/opt/opt_reduce.cc
--- 2/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@@ -43,13 -43,14 +43,14 @@@ struct OptReduceWorke
                        return;
                cells.erase(cell);
  
 -              RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 +              RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+               sig_a.sort_and_unify();
                pool<RTLIL::SigBit> new_sig_a_bits;
  
--              for (auto &bit : sig_a.to_sigbit_set())
++              for (auto &bit : sig_a)
                {
                        if (bit == RTLIL::State::S0) {
 -                              if (cell->type == "$reduce_and") {
 +                              if (cell->type == ID($reduce_and)) {
                                        new_sig_a_bits.clear();
                                        new_sig_a_bits.insert(RTLIL::State::S0);
                                        break;
@@@ -86,8 -87,9 +87,9 @@@
                }
  
                RTLIL::SigSpec new_sig_a(new_sig_a_bits);
+               new_sig_a.sort_and_unify();
  
 -              if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
 +              if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
                        log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
                        did_something = true;
                        total_count++;