Update README.md for (* abc9_required *)

diff --git a/README.md b/README.md
index 77e9410dae48b63b110f1bcca9fcd8c6eadd0df6..043e772ba271ee71ea4396875ed6d8ee0c5bb501 100644 (file)
--- a/README.md
+++ b/README.md
@@ -373,10 +373,15 @@ Verilog Attributes and non-standard features
   `abc9` to preserve the integrity of carry-chains. Specifying this attribute
   onto a bus port will affect only its most significant bit.
 
-- The port attribute ``abc9_arrival`` specifies an integer (for output ports
-  only) to be used as the arrival time of this sequential port. It can be used,
-  for example, to specify the clk-to-Q delay of a flip-flop for consideration
-  during `abc9` techmapping.
+- The output port attribute ``abc9_arrival`` specifies an integer, or a string
+  of space-separated integers to be used as the arrival time of this blackbox
+  port. It can be used, for example, to specify the clk-to-Q delay of a flip-
+  flop output for consideration during `abc9` techmapping.
+
+- The input port attribute ``abc9_requiredl`` specifies an integer, or a string
+  of space-separated integers to be used as the required time of this blackbox
+  port. It can be used, for example, to specify the setup-time of a flip-flop
+  input for consideration during `abc9` techmapping.
 
 - The module attribute ``abc9_flop`` is a boolean marking the module as a
   flip-flop. This allows `abc9` to analyse its contents in order to perform