i965: Add an assertion that writemask != NULL for non-ARFs.

We've observed GPU hangs on Ivybridge from the following instruction:

mov(8) g115<1>.F 0D { align16 WE_normal NoDDChk 1Q };

There should be no reason to ever set the writemask on a destination
register to zero, except for perhaps the ARF NULL register.

This patch adds an assertion to enforce this for non-ARF registers.
Excluding ARFs is conservative yet should still catch the majority
of mistakes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f26c913565882cd30127f9ceac3e53f4fcc24433..36c494ee2b3bbb6a849b6ee677689c4567751ed1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -126,6 +126,8 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
       else {
         insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
         insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
+         assert(dest.dw1.bits.writemask != 0 ||
+                dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
         /* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
          *    Although Dst.HorzStride is a don't care for Align16, HW needs
          *    this to be programmed as "01".