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i2s: Fix the incorrect TX fifo almost empty offset
authorPawel Sagan <psagan@internships.antmicro.com>
Thu, 25 Jun 2020 12:32:50 +0000 (14:32 +0200)
committerMateusz Holenko <mholenko@antmicro.com>
Wed, 1 Jul 2020 11:32:53 +0000 (13:32 +0200)
litex/soc/cores/i2s.py patch | blob | history

diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py
index 14ba84159f46a72bb2e2d087fd8fa63b3a6c38ba..a5dde4ca5cc4cb6b8877cbad25afed7664e020c0 100644 (file)
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@@ -495,7 +495,7 @@ class S7I2S(Module, AutoCSR, AutoDoc):
                 p_DEVICE              = "7SERIES",
                 p_FIFO_SIZE           = "18Kb",
                 p_DATA_WIDTH          = fifo_data_width,
-                p_ALMOST_EMPTY_OFFSET = fifo_depth,
+                p_ALMOST_EMPTY_OFFSET = (512 - fifo_depth),
                 p_ALMOST_FULL_OFFSET  = 8,
                 p_DO_REG              = 0,
                 i_CLK         = ClockSignal(),