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raw | patch | inline | side by side (parent: 3f6c63a)
sim: example-synacor: move libsim.a creation to top-level
authorMike Frysinger <vapier@gentoo.org>
Tue, 27 Dec 2022 02:22:03 +0000 (21:22 -0500)
committerMike Frysinger <vapier@gentoo.org>
Tue, 10 Jan 2023 06:15:24 +0000 (01:15 -0500)
The objects are still compiled in the subdir, but the creation of the
archive itself is in the top-level.  This is a required step before we
can move compilation itself up, and makes it easier to review.

The downside is that each object compile is a recursive make instead of
a single one.  On my 4 core system, it adds ~100msec to the build per
port, so it's not great, but it shouldn't be a big deal.  This will go
away of course once the top-level compiles objects.

sim/Makefile.in patch | blob | history
sim/example-synacor/Makefile.in patch | blob | history
sim/example-synacor/local.mk patch | blob | history

diff --git a/sim/Makefile.in b/sim/Makefile.in
index 0cb3dea34750e56a81f306403a90d69e88cc7187..b5890318cc8ab67371e7848b1700cd456e96a6af 100644 (file)
--- a/sim/Makefile.in
+++ b/sim/Makefile.in
@@ -184,71 +184,72 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 = erc32/run erc32/sis
 @SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 = sim-%D-install-exec-local
 @SIM_ENABLE_ARCH_erc32_TRUE@am__append_44 = sim-erc32-uninstall-local
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_45 = example-synacor/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_46 = frv/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 = frv/eng.h
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 = $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_45 = example-synacor/libsim.a
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_46 = example-synacor/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 = frv/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 = frv/eng.h
 @SIM_ENABLE_ARCH_frv_TRUE@am__append_49 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_50 = ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_51 = h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_52 = iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_50 = $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_51 = ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_52 = h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_53 = iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 = iq2000/eng.h
 @SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_56 = lm32/run
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_57 = lm32/run
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 = lm32/eng.h
 @SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_61 = m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 = $(m32c_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 = \
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_62 = m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 = $(m32c_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 = m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_65 = \
 @SIM_ENABLE_ARCH_m32c_TRUE@    $(m32c_BUILD_OUTPUTS) \
 @SIM_ENABLE_ARCH_m32c_TRUE@    m32c/m32c.c.log \
 @SIM_ENABLE_ARCH_m32c_TRUE@    m32c/r8c.c.log
 
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_65 = m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_66 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_66 = m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 = \
 @SIM_ENABLE_ARCH_m32r_TRUE@    m32r/eng.h \
 @SIM_ENABLE_ARCH_m32r_TRUE@    m32r/engx.h \
 @SIM_ENABLE_ARCH_m32r_TRUE@    m32r/eng2.h
 
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 = $(m32r_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_70 = m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_71 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 = m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_75 = mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_76 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_79 = mips/itable.h \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_70 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_71 = m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 = m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_75 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_76 = mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_77 = microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_79 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = mips/itable.h \
 @SIM_ENABLE_ARCH_mips_TRUE@    $(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_80 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_81 = \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@     $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@     mips/stamp-gen-mode-single
 
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_81 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_82 = \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        mips/stamp-gen-mode-m16-m16 \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        mips/stamp-gen-mode-m16-m32
 
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_82 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_83 = \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@      $(SIM_MIPS_MULTI_SRC) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@      mips/stamp-gen-mode-multi-igen \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@      mips/stamp-gen-mode-multi-run
 
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 = $(mips_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_mips_TRUE@am__append_84 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 = \
 @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@@ -257,29 +258,29 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
 
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 = $(mn10300_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_mn10300_TRUE@am__append_90 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_91 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_92 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_91 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_92 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_93 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
 @SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_98 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_99 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_100 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_101 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 = \
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_97 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run ppc/psim
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_99 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_100 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_101 = rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_102 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = \
 @SIM_ENABLE_ARCH_sh_TRUE@      sh/code.c \
 @SIM_ENABLE_ARCH_sh_TRUE@      sh/ppi.c
 
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 = v850/run
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = \
 @SIM_ENABLE_ARCH_v850_TRUE@    v850/icache.h \
 @SIM_ENABLE_ARCH_v850_TRUE@    v850/idecode.h \
 @SIM_ENABLE_ARCH_v850_TRUE@    v850/semantics.h \
@@ -288,8 +289,8 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_v850_TRUE@    v850/itable.h \
 @SIM_ENABLE_ARCH_v850_TRUE@    v850/engine.h
 
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = $(v850_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_v850_TRUE@am__append_110 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 = $(v850_BUILD_OUTPUTS)
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@@ -486,6 +487,20 @@ erc32_libsim_a_AR = $(AR) $(ARFLAGS)
 @SIM_ENABLE_ARCH_erc32_TRUE@   erc32/modules.o
 am_erc32_libsim_a_OBJECTS =
 erc32_libsim_a_OBJECTS = $(am_erc32_libsim_a_OBJECTS)
+example_synacor_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_DEPENDENCIES =  \
+@SIM_ENABLE_ARCH_examples_TRUE@        $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_examples_TRUE@        $(patsubst \
+@SIM_ENABLE_ARCH_examples_TRUE@        %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_examples_TRUE@        $(patsubst \
+@SIM_ENABLE_ARCH_examples_TRUE@        %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/interp.o \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/modules.o \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/sim-main.o \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/sim-resume.o
+am_example_synacor_libsim_a_OBJECTS =
+example_synacor_libsim_a_OBJECTS =  \
+       $(am_example_synacor_libsim_a_OBJECTS)
 igen_libigen_a_AR = $(AR) $(ARFLAGS)
 igen_libigen_a_LIBADD =
 @SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS =  \
@@ -833,12 +848,12 @@ SOURCES = $(aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
        $(bpf_libsim_a_SOURCES) $(common_libcommon_a_SOURCES) \
        $(cr16_libsim_a_SOURCES) $(cris_libsim_a_SOURCES) \
        $(d10v_libsim_a_SOURCES) $(erc32_libsim_a_SOURCES) \
-       $(igen_libigen_a_SOURCES) $(aarch64_run_SOURCES) \
-       $(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
-       $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
-       $(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
-       $(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
-       $(erc32_run_SOURCES) erc32/sis.c \
+       $(example_synacor_libsim_a_SOURCES) $(igen_libigen_a_SOURCES) \
+       $(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \
+       $(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \
+       $(cr16_run_SOURCES) $(cris_run_SOURCES) \
+       $(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \
+       $(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \
        $(example_synacor_run_SOURCES) $(frv_run_SOURCES) \
        $(ft32_run_SOURCES) $(h8300_run_SOURCES) \
        $(igen_filter_SOURCES) $(igen_gen_SOURCES) \
@@ -1390,33 +1405,33 @@ srcroot = $(srcdir)/..
 SUBDIRS = @subdirs@ $(SIM_SUBDIRS)
 AM_MAKEFLAGS = SIM_NEW_COMMON_OBJS_="$(SIM_NEW_COMMON_OBJS)" \
        $(am__append_3) $(am__append_16) $(am__append_30) \
-       $(am__append_57) $(am__append_66) $(am__append_71) \
-       $(am__append_78) $(am__append_87)
+       $(am__append_58) $(am__append_67) $(am__append_72) \
+       $(am__append_79) $(am__append_88)
 pkginclude_HEADERS = $(am__append_1)
 noinst_LIBRARIES = common/libcommon.a $(am__append_5) $(am__append_8) \
        $(am__append_10) $(am__append_12) $(am__append_14) \
        $(am__append_17) $(am__append_22) $(am__append_28) \
-       $(am__append_35) $(am__append_41)
+       $(am__append_35) $(am__append_41) $(am__append_45)
 BUILT_SOURCES = $(am__append_19) $(am__append_24) $(am__append_32) \
-       $(am__append_37) $(am__append_47) $(am__append_53) \
-       $(am__append_58) $(am__append_67) $(am__append_79) \
-       $(am__append_88) $(am__append_94) $(am__append_103) \
-       $(am__append_108)
+       $(am__append_37) $(am__append_48) $(am__append_54) \
+       $(am__append_59) $(am__append_68) $(am__append_80) \
+       $(am__append_89) $(am__append_95) $(am__append_104) \
+       $(am__append_109)
 CLEANFILES = common/version.c common/version.c-stamp \
        testsuite/common/bits-gen testsuite/common/bits32m0.c \
        testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
        testsuite/common/bits64m63.c
-DISTCLEANFILES = $(am__append_85)
+DISTCLEANFILES = $(am__append_86)
 MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
        %,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \
        $(common_GEN_MODULES_C_TARGETS) $(patsubst \
        %,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_7) \
        site-sim-config.exp testrun.log testrun.sum $(am__append_21) \
        $(am__append_27) $(am__append_34) $(am__append_40) \
-       $(am__append_49) $(am__append_55) $(am__append_60) \
-       $(am__append_64) $(am__append_69) $(am__append_74) \
-       $(am__append_84) $(am__append_90) $(am__append_96) \
-       $(am__append_106) $(am__append_110)
+       $(am__append_50) $(am__append_56) $(am__append_61) \
+       $(am__append_65) $(am__append_70) $(am__append_75) \
+       $(am__append_85) $(am__append_91) $(am__append_97) \
+       $(am__append_107) $(am__append_111)
 AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
 AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
        $(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
@@ -1428,11 +1443,11 @@ LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
 SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
        $(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \
        $(am__append_4) $(am__append_20) $(am__append_25) \
-       $(am__append_33) $(am__append_38) $(am__append_48) \
-       $(am__append_54) $(am__append_59) $(am__append_62) \
-       $(am__append_68) $(am__append_72) $(am__append_83) \
-       $(am__append_89) $(am__append_95) $(am__append_104) \
-       $(am__append_109)
+       $(am__append_33) $(am__append_38) $(am__append_49) \
+       $(am__append_55) $(am__append_60) $(am__append_63) \
+       $(am__append_69) $(am__append_73) $(am__append_84) \
+       $(am__append_90) $(am__append_96) $(am__append_105) \
+       $(am__append_110)
 SIM_INSTALL_DATA_LOCAL_DEPS = 
 SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_43)
 SIM_UNINSTALL_LOCAL_DEPS = $(am__append_44)
@@ -1855,6 +1870,16 @@ testsuite_common_CPPFLAGS = \
 
 @SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32
 @SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES = 
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_examples_TRUE@        $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_examples_TRUE@        $(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_examples_TRUE@        $(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/interp.o \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/modules.o \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/sim-main.o \
+@SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/sim-resume.o
+
 @SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES = 
 @SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \
 @SIM_ENABLE_ARCH_examples_TRUE@        example-synacor/nrun.o \
@@ -2014,8 +2039,8 @@ testsuite_common_CPPFLAGS = \
 @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =  \
 @SIM_ENABLE_ARCH_mips_TRUE@    $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@    mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@    $(am__append_80) $(am__append_81) \
-@SIM_ENABLE_ARCH_mips_TRUE@    $(am__append_82)
+@SIM_ENABLE_ARCH_mips_TRUE@    $(am__append_81) $(am__append_82) \
+@SIM_ENABLE_ARCH_mips_TRUE@    $(am__append_83)
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@@ -2460,6 +2485,14 @@ erc32/libsim.a: $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_DEPENDENCIES) $(EXTRA
        $(AM_V_at)-rm -f erc32/libsim.a
        $(AM_V_AR)$(erc32_libsim_a_AR) erc32/libsim.a $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD)
        $(AM_V_at)$(RANLIB) erc32/libsim.a
+example-synacor/$(am__dirstamp):
+       @$(MKDIR_P) example-synacor
+       @: > example-synacor/$(am__dirstamp)
+
+example-synacor/libsim.a: $(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_DEPENDENCIES) $(EXTRA_example_synacor_libsim_a_DEPENDENCIES) example-synacor/$(am__dirstamp)
+       $(AM_V_at)-rm -f example-synacor/libsim.a
+       $(AM_V_AR)$(example_synacor_libsim_a_AR) example-synacor/libsim.a $(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD)
+       $(AM_V_at)$(RANLIB) example-synacor/libsim.a
 igen/$(am__dirstamp):
        @$(MKDIR_P) igen
        @: > igen/$(am__dirstamp)
@@ -2592,9 +2625,6 @@ erc32/sis.$(OBJEXT): erc32/$(am__dirstamp) \
 @SIM_ENABLE_ARCH_erc32_FALSE@erc32/sis$(EXEEXT): $(erc32_sis_OBJECTS) $(erc32_sis_DEPENDENCIES) $(EXTRA_erc32_sis_DEPENDENCIES) erc32/$(am__dirstamp)
 @SIM_ENABLE_ARCH_erc32_FALSE@  @rm -f erc32/sis$(EXEEXT)
 @SIM_ENABLE_ARCH_erc32_FALSE@  $(AM_V_CCLD)$(LINK) $(erc32_sis_OBJECTS) $(erc32_sis_LDADD) $(LIBS)
-example-synacor/$(am__dirstamp):
-       @$(MKDIR_P) example-synacor
-       @: > example-synacor/$(am__dirstamp)
 
 example-synacor/run$(EXEEXT): $(example_synacor_run_OBJECTS) $(example_synacor_run_DEPENDENCIES) $(EXTRA_example_synacor_run_DEPENDENCIES) example-synacor/$(am__dirstamp)
        @rm -f example-synacor/run$(EXEEXT)
@@ -4022,6 +4052,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
 @SIM_ENABLE_ARCH_erc32_TRUE@   $(LIBTOOL) --mode=install $(INSTALL_PROGRAM) erc32/run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT)
 @SIM_ENABLE_ARCH_erc32_TRUE@sim-erc32-uninstall-local:
 @SIM_ENABLE_ARCH_erc32_TRUE@   rm -f $(DESTDIR)$(bindir)/sis
+@SIM_ENABLE_ARCH_examples_TRUE@$(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD): example-synacor/hw-config.h
+
+@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: example-synacor/%.c
+@SIM_ENABLE_ARCH_examples_TRUE@        $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c
+@SIM_ENABLE_ARCH_examples_TRUE@        $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
 @SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS)
 
 @SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true
diff --git a/sim/example-synacor/Makefile.in b/sim/example-synacor/Makefile.in
index 48713d2c4aaabd12b86c7dab09cd05caf270ee54..cece1e543ca7ac1a4db434a0c27c5828262c3048 100644 (file)
--- a/sim/example-synacor/Makefile.in
+++ b/sim/example-synacor/Makefile.in
@@ -17,10 +17,6 @@
 
 ## COMMON_PRE_CONFIG_FRAG
 
-SIM_OBJS = \
-       $(SIM_NEW_COMMON_OBJS) \
-       sim-resume.o \
-       interp.o \
-       sim-main.o
+SIM_LIBSIM =
 
 ## COMMON_POST_CONFIG_FRAG
diff --git a/sim/example-synacor/local.mk b/sim/example-synacor/local.mk
index 0ca2d1378f6e95a6e2d3c9059c07753395055ad7..9f00eebc26e5b3e0e114072257bca88b1a3bbb62 100644 (file)
--- a/sim/example-synacor/local.mk
+++ b/sim/example-synacor/local.mk
@@ -16,6 +16,25 @@
 ## You should have received a copy of the GNU General Public License
 ## along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
+%C%_libsim_a_SOURCES =
+%C%_libsim_a_LIBADD = \
+       $(common_libcommon_a_OBJECTS) \
+       $(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
+       $(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
+       %D%/interp.o \
+       %D%/modules.o \
+       %D%/sim-main.o \
+       %D%/sim-resume.o
+$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
+
+noinst_LIBRARIES += %D%/libsim.a
+
+%D%/%.o: %D%/%.c
+       $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+%D%/%.o: common/%.c
+       $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
 %C%_run_SOURCES =
 %C%_run_LDADD = \
        %D%/nrun.o \