[ARM, AArch64] Add missing vtst_p16 and vtstq_p16, and vtst_p{8,16} and vtstq_p{8...

2016-05-23  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/arm_neon.h (vtst_p16, vtstq_p16): New.

	gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests for
	vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16.

From-SVN: r236576

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e113f7958f9e13bbae2141246d91d9a31bcf5d2b..27f6c665aeb318100e22d9e007f40ed69c81c4b0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2016-05-23  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       * config/arm/arm_neon.h (vtst_p16, vtstq_p16): New.
+
 2016-05-22  Jakub Jelinek  <jakub@redhat.com>
 
        * config/i386/sse.md (vec_set_lo_<mode><mask_name>,

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 07503d7aa353760117b923da28beacbf61584964..7997cb4ad3a9ac11eaad53696a78d8254630f59a 100644 (file)
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -2607,6 +2607,12 @@ vtst_p8 (poly8x8_t __a, poly8x8_t __b)
   return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b);
 }
 
+__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+vtst_p16 (poly16x4_t __a, poly16x4_t __b)
+{
+  return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b);
+}
+
 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
 vtstq_s8 (int8x16_t __a, int8x16_t __b)
 {
@@ -2649,6 +2655,12 @@ vtstq_p8 (poly8x16_t __a, poly8x16_t __b)
   return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b);
 }
 
+__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+vtstq_p16 (poly16x8_t __a, poly16x8_t __b)
+{
+  return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b);
+}
+
 __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
 vabd_s8 (int8x8_t __a, int8x8_t __b)
 {

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a23d9406087d132eaf5d207432bc36f2e446293d..cc1c39fa55927e929c2e64e7b2212420de5371d1 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-05-23  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests for
+       vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16.
+
 2016-05-22  Jakub Jelinek  <jakub@redhat.com>
 
        * gcc.target/i386/avx512bw-kunpckdq-1.c (avx512bw_test): Use "m"

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
index 9e74ffb150725a301b2cb7541a0f1aacaaa66f52..8f9e6516144806040f8dd4f5e435cfaf8dcedc94 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
@@ -32,6 +32,19 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
 VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
                                                  0x0, 0xffffffff };
 
+/* Expected results with poly input.  */
+VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
+                                            0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
+                                             0xff, 0xff, 0xff, 0xff,
+                                             0xff, 0xff, 0xff, 0xff,
+                                             0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected_poly,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
+VECT_VAR_DECL(expected_poly,uint,16,8) [] = { 0x0, 0xffff,
+                                             0x0, 0xffff,
+                                             0xffff, 0xffff,
+                                             0xffff, 0xffff };
+
 #define INSN_NAME vtst
 #define TEST_MSG "VTST/VTSTQ"
 
@@ -71,12 +84,16 @@ FNNAME (INSN_NAME)
   VDUP(vector2, , uint, u, 8, 8, 15);
   VDUP(vector2, , uint, u, 16, 4, 5);
   VDUP(vector2, , uint, u, 32, 2, 1);
+  VDUP(vector2, , poly, p, 8, 8, 15);
+  VDUP(vector2, , poly, p, 16, 4, 5);
   VDUP(vector2, q, int, s, 8, 16, 15);
   VDUP(vector2, q, int, s, 16, 8, 5);
   VDUP(vector2, q, int, s, 32, 4, 1);
   VDUP(vector2, q, uint, u, 8, 16, 15);
   VDUP(vector2, q, uint, u, 16, 8, 5);
   VDUP(vector2, q, uint, u, 32, 4, 1);
+  VDUP(vector2, q, poly, p, 8, 16, 15);
+  VDUP(vector2, q, poly, p, 16, 8, 5);
 
 #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)     \
   MACRO(VAR, , T1, T2, 8, 8);                                  \
@@ -109,6 +126,18 @@ FNNAME (INSN_NAME)
   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
+
+  /* Now, test the variants with poly8 and poly16 as input.  */
+#undef CMT
+#define CMT " (poly input)"
+  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
+  TEST_BINARY_OP(INSN_NAME, , poly, p, 16, 4);
+  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
+  TEST_BINARY_OP(INSN_NAME, q, poly, p, 16, 8);
+  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_poly, CMT);
 }
 
 int main (void)