+Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
+
+Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
+
+ * gencode.c (write_opcodes): Also write out the format of the
+ opcode.
+ * mn10300_sim.h (simops): Add "format" field.
+ * interp.c (sim_resume): Deal with endianness issues here.
+
Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
* simops.c (REG0_4): Define.
unsigned long mask;
State.regs[REG_SP] += insn & 0xff;
- State.pc = State.regs[REG_MDR] - 3;
sp = State.regs[REG_SP];
mask = (insn & 0xff00) >> 8;
State.regs[REG_D0 + 2] = load_mem (sp, 4);
sp += 4;
}
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_SP] = sp;
+
+ /* Restore the PC value. */
+ State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
+ | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
+ State.pc -= 3;
}
/* retf reg_list,imm8 */
sp = State.regs[REG_SP] + (insn & 0xff);
State.regs[REG_SP] = sp;
- State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
- | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
- State.pc -= 3;
+ State.pc = State.regs[REG_MDR] - 3;
sp = State.regs[REG_SP];
State.regs[REG_D0 + 2] = load_mem (sp, 4);
sp += 4;
}
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_SP] = sp;
}
/* rets */