arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disable

According to the armarm:
ARMv8.1-HPD introduces the facility to disable the hierarchical
attributes, APTable, PXNTable, and UXNTable, in the translation tables.
This disable has no effect on the NSTable bit.  This feature is
mandatory in ARMv8.1 implementations.

This feature is added only to the VMSAv8-64 translation regimes. ARMv8.2
extends this to the AArch32 translation regimes, see ARMv8.2-AA32HPD.

The ID_AA64MMFR1_EL1.HPDS field identifies the support for ARMv8.1-HPD.

Change-Id: Ibbf589b82f2c1e4437b43252f8f633e8f6fb0b80
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19610
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index ea2927d5d3ac04bcb199879f099d1bf706c46123..3d30e5f6e88686c3ee8ce807afcea8fe25441bae 100644 (file)
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2018 ARM Limited
+# Copyright (c) 2012-2013, 2015-2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -105,8 +105,8 @@ class ArmISA(SimObject):
     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
         "AArch64 Memory Model Feature Register 0")
-    # Reserved for future expansion
-    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
+    # HPDS
+    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000001000,
         "AArch64 Memory Model Feature Register 1")
     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
         "AArch64 Memory Model Feature Register 2")

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index d8f2971621b1bd4371851848028a53fc844cee48..508170a556e526777b17162248bd17dac4453214 100644 (file)
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -135,7 +135,7 @@ TableWalker::WalkerState::WalkerState() :
     htcr(0), hcr(0), vtcr(0),
     isWrite(false), isFetch(false), isSecure(false),
     secureLookup(false), rwTable(false), userTable(false), xnTable(false),
-    pxnTable(false), stage2Req(false),
+    pxnTable(false), hpd(false), stage2Req(false),
     stage2Tran(nullptr), timing(false), functional(false),
     mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc),
     delayed(false), tableWalker(nullptr)
@@ -782,6 +782,7 @@ TableWalker::processWalkAArch64()
                 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
                 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
                 tg = GrainMap_tg0[currState->tcr.tg0];
+                currState->hpd = currState->tcr.hpd0;
                 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
                     currState->tcr.epd0)
                   fault = true;
@@ -791,6 +792,7 @@ TableWalker::processWalkAArch64()
                 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
                 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
                 tg = GrainMap_tg1[currState->tcr.tg1];
+                currState->hpd = currState->tcr.hpd1;
                 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
                     currState->tcr.epd1)
                   fault = true;
@@ -809,6 +811,8 @@ TableWalker::processWalkAArch64()
             ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
             tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
             tg = GrainMap_tg0[currState->tcr.tg0];
+            currState->hpd = currState->hcr.e2h ?
+                currState->tcr.hpd0 : currState->tcr.hpd;
             break;
 
           case 0xffff:
@@ -816,6 +820,7 @@ TableWalker::processWalkAArch64()
             ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
             tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
             tg = GrainMap_tg1[currState->tcr.tg1];
+            currState->hpd = currState->tcr.hpd1;
             if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
                 currState->tcr.epd1 || !currState->hcr.e2h)
               fault = true;
@@ -834,6 +839,7 @@ TableWalker::processWalkAArch64()
                 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
                 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
                 tg = GrainMap_tg0[currState->tcr.tg0];
+                currState->hpd = currState->tcr.hpd;
                 break;
             default:
                 // invalid addr if top two bytes are not all 0s
@@ -1640,13 +1646,13 @@ TableWalker::doLongDescriptor()
             currState->secureLookup = currState->secureLookup &&
                 currState->longDesc.secureTable();
             currState->rwTable = currState->rwTable &&
-                currState->longDesc.rwTable();
+                (currState->longDesc.rwTable() || currState->hpd);
             currState->userTable = currState->userTable &&
-                currState->longDesc.userTable();
+                (currState->longDesc.userTable() || currState->hpd);
             currState->xnTable = currState->xnTable ||
-                currState->longDesc.xnTable();
+                (currState->longDesc.xnTable() && !currState->hpd);
             currState->pxnTable = currState->pxnTable ||
-                currState->longDesc.pxnTable();
+                (currState->longDesc.pxnTable() && !currState->hpd);
 
             // Set up next level lookup
             Addr next_desc_addr = currState->longDesc.nextDescAddr(

diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 3b601436673c004f0874699ae2d58c58c6069a23..2fc45ceafa518f47606aed4a37f36a45947461ac 100644 (file)
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2016 ARM Limited
+ * Copyright (c) 2010-2016, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -764,6 +764,9 @@ class TableWalker : public ClockedObject
         bool xnTable;
         bool pxnTable;
 
+        /** Hierarchical access permission disable */
+        bool hpd;
+
         /** Flag indicating if a second stage of lookup is required */
         bool stage2Req;