radv/gfx10: implement radv_emit_fb_ds_state()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 708905ba2a4f751aedc912ffc63c6809f1ac11ef..43aec5a4a78609b20cc2e00af50c7b05330c0db5 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1411,8 +1411,26 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
        radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
        radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
 
-
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
+               radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
+
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
+               radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
+               radeon_emit(cmd_buffer->cs, db_z_info);
+               radeon_emit(cmd_buffer->cs, db_stencil_info);
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
+
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
+               radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
+       } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
                radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
                radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));