i965: Use SENDC on the first render target write on gen6.

This is apparently required, as the thread will be initiated while it
still has dependencies, and this is what waits for those to be
resolved before writing color.

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 9633c95ff50a8fc7d8e8162fc7736b6e9173ad60..6c3db61035a8d3f9258b5098d41e02f5dd42d18a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -551,6 +551,7 @@
 #define BRW_OPCODE_POP        47
 #define BRW_OPCODE_WAIT       48
 #define BRW_OPCODE_SEND       49
+#define BRW_OPCODE_SENDC      50
 #define BRW_OPCODE_MATH       56
 #define BRW_OPCODE_ADD        64
 #define BRW_OPCODE_MUL        65

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 12b8f2e46787c79b52f3e6765624f2fd66502579..57972626128fcd698da5fce6da60d9254ee32ecf 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -72,6 +72,7 @@ struct {
     [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
 
     [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
+    [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
     [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
     [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
@@ -876,7 +877,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
        string (file, " ");
        err |= control (file, "function", math_function,
                        inst->header.destreg__conditionalmod, NULL);
-    } else if (inst->header.opcode != BRW_OPCODE_SEND)
+    } else if (inst->header.opcode != BRW_OPCODE_SEND &&
+              inst->header.opcode != BRW_OPCODE_SENDC)
        err |= control (file, "conditional modifier", conditional_modifier,
                        inst->header.destreg__conditionalmod, NULL);
 
@@ -907,7 +909,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
        err |= src1 (file, inst);
     }
 
-    if (inst->header.opcode == BRW_OPCODE_SEND) {
+    if (inst->header.opcode == BRW_OPCODE_SEND ||
+       inst->header.opcode == BRW_OPCODE_SENDC) {
        int target;
 
        if (gen >= 6)
@@ -1070,7 +1073,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
        err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
        if (gen >= 6)
            err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
-       if (inst->header.opcode == BRW_OPCODE_SEND)
+       if (inst->header.opcode == BRW_OPCODE_SEND ||
+           inst->header.opcode == BRW_OPCODE_SENDC)
            err |= control (file, "end of thread", end_of_thread,
                            inst->bits3.generic.end_of_thread, &space);
        if (space)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index d5f24c263fbc3b34f5a90019ba97c436bba4c8db..3744e813bb34201b3b25da987ff16b59f1c77cf6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1735,7 +1735,11 @@ void brw_fb_WRITE(struct brw_compile *p,
    GLuint msg_control, msg_type;
    GLboolean header_present = GL_TRUE;
 
-   insn = next_insn(p, BRW_OPCODE_SEND);
+   if (intel->gen >= 6 && binding_table_index == 0) {
+      insn = next_insn(p, BRW_OPCODE_SENDC);
+   } else {
+      insn = next_insn(p, BRW_OPCODE_SEND);
+   }
    /* The execution mask is ignored for render target writes. */
    insn->header.predicate_control = 0;
    insn->header.compression_control = BRW_COMPRESSION_NONE;