Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/CHANGELOG b/CHANGELOG
index c1ffaa44a18030ad9630a65c2904531d6644d50f..51d5e1dc942c376fc9a94e6b2ebb624afc309735 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
+    - Added support for SystemVerilog typedefs
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------

diff --git a/README.md b/README.md
index fdd4bb410d54f59f30016c0d990a459f27112b74..db7810cb4f51d9bed1339e9549169a2f3d4ad713 100644 (file)
--- a/README.md
+++ b/README.md
@@ -510,6 +510,8 @@ from SystemVerilog:
   into a design with ``read_verilog``, all its packages are available to
   SystemVerilog files being read into the same design afterwards.
 
+- typedefs are supported (including inside packages)
+
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.