Now that we clear the PITCHALIGN" field when filling GMEM input attachment
descriptors, we can get rid of the extra tile width alignment on a630/a640.
With the "block_align_shift" value change, this brings down the default
gmem_align from 16k to 4k on a630/a640 and down from 24k to 12k on a650,
to match the gallium driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5528>
case 618:
device->ccu_offset_gmem = 0x7c000; /* 0x7e000 in some cases? */
device->ccu_offset_bypass = 0x10000;
- device->tile_align_w = 64;
+ device->tile_align_w = 32;
device->magic.PC_UNKNOWN_9805 = 0x0;
device->magic.SP_UNKNOWN_A0F8 = 0x0;
break;
case 640:
device->ccu_offset_gmem = 0xf8000;
device->ccu_offset_bypass = 0x20000;
- device->tile_align_w = 64;
+ device->tile_align_w = 32;
device->magic.PC_UNKNOWN_9805 = 0x1;
device->magic.SP_UNKNOWN_A0F8 = 0x1;
break;
tu_render_pass_gmem_config(struct tu_render_pass *pass,
const struct tu_physical_device *phys_dev)
{
- uint32_t block_align_shift = 4; /* log2(gmem_align/(tile_align_w*tile_align_h)) */
+ uint32_t block_align_shift = 3; /* log2(gmem_align/(tile_align_w*tile_align_h)) */
uint32_t tile_align_w = phys_dev->tile_align_w;
uint32_t gmem_align = (1 << block_align_shift) * tile_align_w * TILE_ALIGN_H;