Sensitive to CEB CEM CEP polarity

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 16a098fd0bc07949da523c42e97217268ff847b7..38b1a12be642788713dc4d4121ead1cb94f5d298 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -84,8 +84,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                        if (st.ffAmux) {
                                SigSpec Y = st.ffAmux->getPort("\\Y");
                                SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B");
-                               A.replace(Y, AB);
                                SigSpec S = st.ffAmux->getPort("\\S");
+                               A.replace(Y, AB);
                                cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S));
                        }
                        else
@@ -101,9 +101,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                        B.replace(Q, D);
                        if (st.ffBmux) {
                                SigSpec Y = st.ffBmux->getPort("\\Y");
-                               SigSpec AB = st.ffBmux->getPort(st.ffBmuxAB == "\\A" ? "\\B" : "\\A");
+                               SigSpec AB = st.ffBmux->getPort(st.ffBenpol ? "\\A" : "\\B");
+                               SigSpec S = st.ffBmux->getPort("\\S");
                                B.replace(Y, AB);
-                               cell->setPort("\\CEB2", st.ffBmux->getPort("\\S"));
+                               cell->setPort("\\CEB2", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
                        }
                        else
                                cell->setPort("\\CEB2", State::S1);
@@ -113,7 +114,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                }
                if (st.ffM) {
                        if (st.ffMmux) {
-                               cell->setPort("\\CEM", st.ffMmux->getPort("\\S"));
+                               SigSpec S = st.ffMmux->getPort("\\S");
+                               cell->setPort("\\CEM", st.ffMenpol ? S : pm.module->Not(NEW_ID, S));
                                pm.autoremove(st.ffMmux);
                        }
                        else
@@ -127,7 +129,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                }
                if (st.ffP) {
                        if (st.ffPmux) {
-                               cell->setPort("\\CEP", st.ffPmux->getPort("\\S"));
+                               SigSpec S = st.ffPmux->getPort("\\S");
+                               cell->setPort("\\CEP", st.ffPenpol ? S : pm.module->Not(NEW_ID, S));
                                st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
                        }
                        else

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 5799358697b6df469f8afc19e59c8b7137e9d16a..a86501d2912d57327a7be5da445aa21aabf56637 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,8 +2,8 @@ pattern xilinx_dsp
 
 state <SigBit> clock
 state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
-state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
-state <bool> ffAenpol
+state <IdString> postAddAB postAddMuxAB
+state <bool> ffAenpol ffBenpol ffMenpol ffPenpol
 
 match dsp
        select dsp->type.in(\DSP48E1)
@@ -112,9 +112,10 @@ match ffBmux
        filter GetSize(port(ffBmux, \Y)) >= GetSize(sigB)
        slice offset GetSize(port(ffBmux, \Y))
        filter offset+GetSize(sigB) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, \Y).extract(offset, GetSize(sigB)) == sigB
-       choice <IdString> AB {\A, \B}
-       filter offset+GetSize(sigffBmux) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, AB).extract(offset, GetSize(sigffBmux)) == sigffBmux
-       set ffBmuxAB AB
+       choice <IdString> BA {\B, \A}
+       filter offset+GetSize(sigffBmux) <= GetSize(port(ffBmux, \Y)) && port(ffBmux, BA).extract(offset, GetSize(sigffBmux)) == sigffBmux
+       define <bool> pol (BA == \B)
+       set ffBenpol pol
        semioptional
 endmatch
 
@@ -122,10 +123,11 @@ match ffMmux
        select ffMmux->type.in($mux)
        select nusers(port(ffMmux, \Y)) == 2
        filter GetSize(port(ffMmux, \Y)) <= GetSize(sigM)
-       choice <IdString> AB {\A, \B}
-       filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
-       filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
-       set ffMmuxAB AB
+       choice <IdString> BA {\B, \A}
+       filter port(ffMmux, BA) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
+       filter nusers(sigM.extract_end(GetSize(port(ffMmux, BA)))) <= 1
+       define <bool> pol (BA == \B)
+       set ffMenpol pol
        optional
 endmatch
 
@@ -144,7 +146,7 @@ match ffM
        filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
        filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
        // Check ffMmux (when present) is a $dff enable mux
-       filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMmuxAB == \A ? \B : \A)
+       filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMenpol ? \A : \B)
        optional
 endmatch
 
@@ -208,16 +210,17 @@ match ffPmux
        select ffPmux->type.in($mux)
        select nusers(port(ffPmux, \Y)) == 2
        filter GetSize(port(ffPmux, \Y)) <= GetSize(sigP)
-       choice <IdString> AB {\A, \B}
-       filter port(ffPmux, AB) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
-       filter nusers(sigP.extract_end(GetSize(port(ffPmux, AB)))) <= 1
-       set ffPmuxAB AB
+       choice <IdString> BA {\B, \A}
+       filter port(ffPmux, BA) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
+       filter nusers(sigP.extract_end(GetSize(port(ffPmux, BA)))) <= 1
+       define <bool> pol (BA == \B)
+       set ffPenpol pol
        optional
 endmatch
 
 code sigP
        if (ffPmux)
-               sigP.replace(port(ffPmux, ffPmuxAB), port(ffPmux, \Y));
+               sigP.replace(port(ffPmux, ffPenpol ? \A : \B), port(ffPmux, \Y));
 endcode
 
 match ffP
@@ -229,7 +232,7 @@ match ffP
        slice offset GetSize(port(ffP, \D))
        filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
        // Check ffPmux (when present) is a $dff enable mux
-       filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPmuxAB == \A ? \B : \A)
+       filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPenpol ? \A : \B)
        optional
 endmatch