improve RX timings (make valid synchronous)

diff --git a/liteeth/common.py b/liteeth/common.py
index b94ce217559a7870891ce97f8350991c67b7e344..1cec3e4e109d5d3f6ab66be6996994fe5d6373cf 100644 (file)
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -7,8 +7,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.record import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import chooser
-from migen.flow.actor import EndpointDescription
-from migen.flow.actor import Sink, Source
+from migen.flow.actor import *
+from migen.flow.plumbing import Buffer
 from migen.actorlib.structuring import Converter, Pipeline
 from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
 from migen.bank.description import *

diff --git a/liteeth/core/arp/__init__.py b/liteeth/core/arp/__init__.py
index ff2b2ac6c5227cee1782167e721f319856f49bb9..fbc31da0848cf8c91f258640ecd787fb31b5caf4 100644 (file)
--- a/liteeth/core/arp/__init__.py
+++ b/liteeth/core/arp/__init__.py
@@ -96,7 +96,7 @@ class LiteEthARPRX(Module):
                        )
                )
                valid = Signal()
-               self.comb += valid.eq(
+               self.sync += valid.eq(
                        depacketizer.source.stb &
                        (depacketizer.source.hwtype == arp_hwtype_ethernet) &
                        (depacketizer.source.proto == arp_proto_ip) &

diff --git a/liteeth/core/icmp/__init__.py b/liteeth/core/icmp/__init__.py
index 5af0f4b42f1b3ebee85a242586c12865a2cebf6e..d2e0abe4c4a44497d7ceef99ff9d653f1a0db056 100644 (file)
--- a/liteeth/core/icmp/__init__.py
+++ b/liteeth/core/icmp/__init__.py
@@ -71,7 +71,7 @@ class LiteEthICMPRX(Module):
                        )
                )
                valid = Signal()
-               self.comb += valid.eq(
+               self.sync += valid.eq(
                        depacketizer.source.stb &
                        (sink.protocol == icmp_protocol)
                )

diff --git a/liteeth/core/ip/__init__.py b/liteeth/core/ip/__init__.py
index 0995596693c113cfc2e0bde9610f040ef43bf124..47cd1359772768c5a538a0391b29bb91e3010068 100644 (file)
--- a/liteeth/core/ip/__init__.py
+++ b/liteeth/core/ip/__init__.py
@@ -136,7 +136,7 @@ class LiteEthIPRX(Module):
                        )
                )
                valid = Signal()
-               self.comb += valid.eq(
+               self.sync += valid.eq(
                        depacketizer.source.stb &
                        (depacketizer.source.target_ip == ip_address) &
                        (depacketizer.source.version == 0x4) &

diff --git a/liteeth/core/udp/__init__.py b/liteeth/core/udp/__init__.py
index f4df2e5e658fda8f1b1c66e85220a09d9945023d..7a8ae5f0140eda4d51d3934024b123d3c6a08fe9 100644 (file)
--- a/liteeth/core/udp/__init__.py
+++ b/liteeth/core/udp/__init__.py
@@ -72,7 +72,7 @@ class LiteEthUDPRX(Module):
                        )
                )
                valid = Signal()
-               self.comb += valid.eq(
+               self.sync += valid.eq(
                        depacketizer.source.stb &
                        (sink.protocol == udp_protocol)
                )