use csr_data_width of 32 to speed up data mila upload

diff --git a/lib/sata/phy/__init__.py b/lib/sata/phy/__init__.py
index 98afb13c5c17dbe4965f91e1cf976e1d3123fa16..925d7720f8e8f0f42a42ebac7d322420865b037b 100644 (file)
--- a/lib/sata/phy/__init__.py
+++ b/lib/sata/phy/__init__.py
@@ -1,5 +1,5 @@
 from lib.sata.common import *
-from lib.sata.phy.ctrl import SATAPHYHostCtrl, SATAPHYDeviceCtrl
+from lib.sata.phy.ctrl import SATAPHYHostCtrl
 from lib.sata.phy.datapath import SATAPHYDatapath
 
 class SATAPHY(Module):

diff --git a/targets/bist.py b/targets/bist.py
index 0e101543cd8a2bbb3bf6c71879d8ade9c189e231..e1b562fd836486e5c0aa0c5eab7ad0bcbcdd0d29 100644 (file)
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -54,7 +54,7 @@ class _CRG(Module):
 
 class GenSoC(Module):
        csr_base = 0x00000000
-       csr_data_width = 8
+       csr_data_width = 32
        csr_map = {
                "uart2wb":                      0,
                "identifier":           2,

diff --git a/test/config.py b/test/config.py
index c27ac82141dc93d8f557a06875aea8b8c809564f..5b274b23829b82333645f7995cea528f87aca16f 100644 (file)
--- a/test/config.py
+++ b/test/config.py
@@ -1,7 +1,7 @@
 from miscope.host.uart2wishbone import Uart2Wishbone
 
 csr_csv_file = "./csr.csv"
-busword = 8
+busword = 32
 debug_wb = False
 
 com = 2