{"armv8.5-a", AARCH64_ARCH_V8_5},
{"armv8.6-a", AARCH64_ARCH_V8_6},
{"armv8.7-a", AARCH64_ARCH_V8_7},
+ {"armv8.8-a", AARCH64_ARCH_V8_8},
{"armv8-r", AARCH64_ARCH_V8_R},
{"armv9-a", AARCH64_ARCH_V9},
{NULL, AARCH64_ARCH_NONE}
instruction which will not execute on the target architecture. The
following architecture names are recognized: @code{armv8-a},
@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
-@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8-r}, and
-@code{armv9-a}.
+@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a},
+@code{armv8-r}, and @code{armv9-a}.
If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}. If neither are
--- /dev/null
+# objdump: -dr
+#...
--- /dev/null
+ .arch armv8.8-a
+
+ ld64b x0, [x1]
+ dsb oshnxs
+ msr hcrx_el2, x0
#define AARCH64_FEATURE_V9 (1ULL << 56) /* Armv9.0-A processors. */
#define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */
#define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */
+#define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */
/* Crypto instructions are the combination of AES and SHA2. */
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \
AARCH64_FEATURE_V8_7 \
| AARCH64_FEATURE_LS64)
+#define AARCH64_ARCH_V8_8 AARCH64_FEATURE (AARCH64_ARCH_V8_7, \
+ AARCH64_FEATURE_V8_8)
#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
AARCH64_FEATURE_V8_R) \
& ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))