connect (new) reset signal on IOPads which comes from the nmigen Pin.

this had to be done because otherwise the IOPads are unstable.
next experiment is to hook ResetSignal(dramsync) with the firmware-driven
reset, which should allow the IOpads - and DQS - to fully stabilise
(oh, and also allow retries on setting them up)

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index e6e0fb177d03dda095d98d731f6450cd2754eaf3..d7d68b4788e9a068c1faf6ce1de6f311c45038d7 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -224,6 +224,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         # Clock --------------------------------------------------------------------------------
         m.d.comb += [
             self.pads.clk.o_clk.eq(ClockSignal("dramsync")),
+            self.pads.clk.o_prst.eq(ResetSignal("dramsync")),
             self.pads.clk.o_fclk.eq(ClockSignal("dramsync2x")),
         ]
         for i in range(len(self.pads.clk.o0)):
@@ -237,6 +238,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         # Addresses and Commands ---------------------------------------------------------------
         m.d.comb += [
             self.pads.a.o_clk.eq(ClockSignal("dramsync")),
+            self.pads.a.o_prst.eq(ResetSignal("dramsync")),
             self.pads.a.o_fclk.eq(ClockSignal("dramsync2x")),
             self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
             self.pads.ba.o_fclk.eq(ClockSignal("dramsync2x")),
@@ -278,6 +280,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             else:
                 m.d.comb += [
                     pad.o_clk.eq(ClockSignal("dramsync")),
+                    pad.o_prst.eq(ResetSignal("dramsync")),
                     pad.o_fclk.eq(ClockSignal("dramsync2x")),
                 ]
             if name == "reset":