soc: use new ModuleTransformer API

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 3a8c5617f7712f5b632711a7fd050f359da1b70b..2097c54efe3b2632b542a64d11585dca8516101c 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -61,7 +61,7 @@ class SDRAMSoC(SoC):
                                from mibuild.xilinx.vivado import XilinxVivadoToolchain
                                if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
                                        from migen.fhdl.simplify import FullMemoryWE
-                                       self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
+                                       self.submodules.wishbone2lasmi = FullMemoryWE()(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
                                else:
                                        self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
                                self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)