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Merge pull request #277 from railnova/feature/vivado_sysverilog_support
authorenjoy-digital <florent@enjoy-digital.fr>
Thu, 10 Oct 2019 17:31:09 +0000 (19:31 +0200)
committerGitHub <noreply@github.com>
Thu, 10 Oct 2019 17:31:09 +0000 (19:31 +0200)
[feature] Add SystemVerilog support for the Vivado builder


Trivial merge