Fix infinite writebacks bug in cache.

src/mem/cache/cache_impl.hh:
    Make sure to pop the list.  Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
    Add an assert as sanity check in case .full() stops working again.

--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 00fecc2b7e67562d7b5bd4ffde979261dddde527..46f4b0ebe198ce0ed6db6c2259e51704d51fe85d 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -326,6 +326,7 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
                                    writebacks, pkt);
             while (!writebacks.empty()) {
                     missQueue->doWriteback(writebacks.front());
+                    writebacks.pop_front();
             }
         }
         missQueue->handleResponse(pkt, curTick + hitLatency);

diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index e54f7aa0840a737f03d5153bf052f7b8ff8fc809..bd966752908f157ceda7413cfd478760512ef546 100644 (file)
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -128,6 +128,7 @@ MSHR*
 MSHRQueue::allocate(Packet * &pkt, int size)
 {
     Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1);
+    assert(!freeList.empty());
     MSHR *mshr = freeList.front();
     assert(mshr->getNumTargets() == 0);
     freeList.pop_front();