Added support for SystemVerilog packages with localparam definitions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 3ba97ed9b91356cc8682faa73d2b9b0d725aad76..ba02dd4c5ec8acf17a47352049613ace183a5f10 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -151,6 +151,7 @@ std::string AST::type2str(AstNodeType type)
        X(AST_POSEDGE)
        X(AST_NEGEDGE)
        X(AST_EDGE)
+       X(AST_PACKAGE)
 #undef X
        default:
                log_abort();
@@ -996,6 +997,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
                        for (auto n : global_decls)
                                (*it)->children.push_back(n->clone());
 
+                       for (auto n : design->packages){
+                               for (auto o : n->children) {
+                                       AstNode *cloned_node = o->clone();
+                                       cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
+                                       (*it)->children.push_back(cloned_node);
+                               }
+                       }
+
                        if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
                                (*it)->str = (*it)->str.substr(1);
 
@@ -1013,6 +1022,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 
                        design->add(process_module(*it, defer));
                }
+               else if ((*it)->type == AST_PACKAGE){
+                       design->packages.push_back((*it)->clone());
+               }
                else
                        global_decls.push_back(*it);
        }

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 21c3ba3c6526082cd148cc908981ec10f4730150..3dcd32bd4fdc0a151ea0d7a0a02612433e91b6e8 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -137,7 +137,9 @@ namespace AST
 
                AST_POSEDGE,
                AST_NEGEDGE,
-               AST_EDGE
+               AST_EDGE,
+
+               AST_PACKAGE
        };
 
        // convert an node type to a string (e.g. for debug output)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 0e5029eb40ef978cf021c99a13012e27ddcd4c3b..3e359170b350563d278e6146998a5c88fb625976 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -806,6 +806,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        case AST_GENBLOCK:
        case AST_GENIF:
        case AST_GENCASE:
+       case AST_PACKAGE:
                break;
 
        // remember the parameter, needed for example in techmap

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 69a8ddaad2d46546d383d5e542d2018b5deda436..107a2dfddd237e770c5a849ff4deb4569003b06a 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -141,6 +141,8 @@ YOSYS_NAMESPACE_END
 "endfunction"  { return TOK_ENDFUNCTION; }
 "task"         { return TOK_TASK; }
 "endtask"      { return TOK_ENDTASK; }
+"package"      { SV_KEYWORD(TOK_PACKAGE); }
+"endpackage"   { SV_KEYWORD(TOK_ENDPACKAGE); }
 "parameter"    { return TOK_PARAMETER; }
 "localparam"   { return TOK_LOCALPARAM; }
 "defparam"     { return TOK_DEFPARAM; }
@@ -351,6 +353,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 "<<<" { return OP_SSHL; }
 ">>>" { return OP_SSHR; }
 
+"::"  { SV_KEYWORD(TOK_PACKAGESEP); }
+
 "+:" { return TOK_POS_INDEXED; }
 "-:" { return TOK_NEG_INDEXED; }
 

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f9584913308a9f0fbb92b1453e0012636aa9b9b0..b46cdd38f07b46a9f6b64269ea785359367532bb 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -102,6 +102,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token <string> TOK_STRING TOK_ID TOK_CONST TOK_REALVAL TOK_PRIMITIVE
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
+%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
@@ -155,6 +156,7 @@ design:
        task_func_decl design |
        param_decl design |
        localparam_decl design |
+       package design |
        /* empty */;
 
 attr:
@@ -212,6 +214,14 @@ hierarchical_id:
        TOK_ID {
                $$ = $1;
        } |
+       hierarchical_id TOK_PACKAGESEP TOK_ID {
+               if ($3->substr(0, 1) == "\\")
+                       *$1 += "::" + $3->substr(1);
+               else
+                       *$1 += "::" + *$3;
+               delete $3;
+               $$ = $1;
+       } |
        hierarchical_id '.' TOK_ID {
                if ($3->substr(0, 1) == "\\")
                        *$1 += "." + $3->substr(1);
@@ -311,6 +321,25 @@ module_arg:
                do_not_require_port_stubs = true;
        };
 
+package:
+       attr TOK_PACKAGE TOK_ID {
+               AstNode *mod = new AstNode(AST_PACKAGE);
+               ast_stack.back()->children.push_back(mod);
+               ast_stack.push_back(mod);
+               current_ast_mod = mod;
+               mod->str = *$3;
+               append_attr(mod, $1);
+       } ';' package_body TOK_ENDPACKAGE {
+               ast_stack.pop_back();
+               current_ast_mod = NULL;
+       };
+
+package_body:
+       package_body package_body_stmt |;
+
+package_body_stmt:
+       localparam_decl;
+
 non_opt_delay:
        '#' '(' expr ')' { delete $3; } |
        '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index bcd87d3fffdecb199bc706689bb2aac140253201..9e09d9f042e3c11dcf8d1b132845f67541683a21 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -304,6 +304,8 @@ RTLIL::Design::~Design()
 {
        for (auto it = modules_.begin(); it != modules_.end(); ++it)
                delete it->second;
+       for (auto n : packages)
+               delete n;
 }
 
 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 940e36ab36074ced267dfadc4a19ab8b8740c4dc..275ba6820d998b88be212135cba940d425e5b49e 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -18,6 +18,7 @@
  */
 
 #include "kernel/yosys.h"
+#include "frontends/ast/ast.h"
 
 #ifndef RTLIL_H
 #define RTLIL_H
@@ -792,6 +793,7 @@ struct RTLIL::Design
 
        int refcount_modules_;
        dict<RTLIL::IdString, RTLIL::Module*> modules_;
+       std::vector<AST::AstNode*> packages;
 
        std::vector<RTLIL::Selection> selection_stack;
        dict<RTLIL::IdString, RTLIL::Selection> selection_vars;